未定义的输出

时间:2017-04-03 14:52:27

标签: vhdl exponent

每次我模拟下面的代码时,我的输出都是未定义的,我不知道为什么。我在代码和模拟中都有数字库。如果有人能帮忙告诉我。此外,模拟中的输入变为00000..000而不是15和3的输入。

MODULE CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

USE ieee.numeric_std.ALL;

entity EXPONENT_FUNCTION is
    Port ( A : in  STD_LOGIC_VECTOR (23 downto 0);
       B : in  STD_LOGIC_VECTOR (23 downto 0);
       O : out STD_LOGIC_VECTOR (47 downto 0));
end EXPONENT_FUNCTION;

architecture Behavioral of EXPONENT_FUNCTION is


signal AIN, BIN, F : integer;
signal u : std_logic_vector (47 downto 0);

begin

AIN <= to_integer(signed (A));

BIN <= to_integer(signed (B));

F <= ((AIN)**(BIN));
u <= std_logic_vector(to_signed(F, 48));
O <= u;


end Behavioral;

模拟代码:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY EXPONENT_TEST IS
END EXPONENT_TEST;

ARCHITECTURE behavior OF EXPONENT_TEST IS 



    COMPONENT EXPONENT_FUNCTION
    PORT(
         A : IN  std_logic_vector(23 downto 0);
         B : IN  std_logic_vector(23 downto 0);
         O : OUT  std_logic_vector(47 downto 0)
        );
    END COMPONENT;



   signal A : std_logic_vector(23 downto 0) := (others => '0');
   signal B : std_logic_vector(23 downto 0) := (others => '0');


   signal O : std_logic_vector(47 downto 0);

   BEGIN

   uut: EXPONENT_FUNCTION PORT MAP (
          A => A,
          B => B,
          O => O
        );


   stim_proc: process
   begin        
   A <= "000000000000000000001111";
    B <= "000000000000000000000011";
      wait for 100 ns;  


       wait;
   end process;

END;

1 个答案:

答案 0 :(得分:0)

您有未定义输出的原因是您有运行时错误。这是因为指数运算符不能与负整数一起使用。如果您将类型更改为naturalunsigned,则会编译并运行:

architecture Behavioral of EXPONENT_FUNCTION is

  signal AIN, BIN, F : natural;
  signal u : std_logic_vector (47 downto 0);

begin

  AIN <= to_integer(unsigned (A));
  BIN <= to_integer(unsigned (B));

  F <= ((AIN)**(BIN));
  u <= std_logic_vector(to_unsigned(F, 48));
  O <= u;

end Behavioral;

https://www.edaplayground.com/x/6F3H