Question

我在编码时遇到语法错误很困难。任何帮助将不胜感激。我的合成器说错误位于blowoncompon＆gt; =的状态但是我认为错误在其他地方，因为当我提交代码状态时，错误会转移到下一个状态。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity question4 is
 Port (
 --System Clock Declaration--------------------------
 clk: in std_logic;

 --Button Inputs-------------------------------------
 btnL: in std_logic; --
 btnU: in std_logic; --Clear
 btnD: in std_logic; --Reset

 sw: in std_logic_vector(7 downto 0);
 led: out std_logic_vector(15 downto 0)
 );
 end question4;

 architecture Behavioral of question4 is 

 constant active: std_logic := '1'; 
 constant bloweron: std_logic_vector(15 downto 0) := "000000011111111";
 constant compon: std_logic_vector(15 downto 0) := "1111111000000000";
 signal clear: std_logic := btnU; 
 signal reset: std_logic := btnD; 


 type states is (blowoncompoff, 
                blowoffcompoff, 
                blowoncompon);

 signal CurrentState: states; 
 signal NextState: states; 

begin 

motorstatetrans: process(currentsate)
begin

    if clear = active then 
        currentstate <= blowoffcompoff; 
    end if; 

    case currentstate is

       when blowoncompon>=   --------Why syntax error near here
            led <= bloweron;  
            led <= compon;

            if currenttemp=settemp then
                Nextstate <= blowoncompoff;

            elsif
                currenttemp>settemp then 
                    Nextstate <= bloweroncompon; 
            end if; 

       when blowoncompoff >= 
            led <= bloweron; 

            if currenttemp < settemp then 
                Nextstate <= bloweroncompon; 

            elsif current temp = set temp then 
                Nextstate <= blowoffcompoff; 

      when blowoffcompoff >=

            if current temp < settemp then 
                Nextstate <= blowoncompon; 

    end case; 
end process;

Answer 1

when blowoncompon>=   --------Why syntax error near here

这不是VHDL语法，就像错误说的那样。只需google it：VHDL Case Statement

when blowoncompon =>

但是你的代码遗漏了很多end if;，所以它仍然无效。

Answer 2

根据其实体声明（clk），您的状态机可能是同步电路。但是你的设计不是同步设计：它不使用它的时钟。

状态机中的VHDL synax错误

2 个答案: