Question

我使用以下逻辑在Verilog的双模预测器中实现2位饱和计数器，我也使用了如下的验证器：

• For each branch, maintain a 2-bit saturating counter:
-if the branch is taken: counter = min(3,counter+1)
-if the branch is not taken: counter = max(0,counter-1)
• If (counter >= 2), predict taken, else predict not taken

module Bimodal(
input clk,
input reset,
input taken, //from ALU unit in execute stage
input branch, //from control unit in decode stage
input [31:0] instrAddr, // current address taken from fetch/decode stage
output reg predicted_taken_or_not);

reg [1:0] saturating_counter [0:1023];


integer i;
parameter max_val = 3 ;
parameter min_val = 0 ;

assign predicted_taken_or_not = saturating_counter[instrAddr[11:2]]>= 2'd2 && branch? 1'd1 : 1'd0;


// write ports to update the 2-bit saturating counter
always @(posedge clk) begin

if(reset) begin
 for(int i=0; i<1024; i++) begin
    saturating_counter[i] = 2'd1;
 end
end

else if (taken) begin
if(max_val>saturating_counter[instrAddr[11:2]]+1)
    saturating_counter[instrAddr[11:2]]<=saturating_counter[instrAddr[11:2]]+1;
else
    saturating_counter[instrAddr[11:2]]<=max_val;
end

else if (~taken) begin
if(min_val>saturating_counter[instrAddr[11:2]]-1)
   saturating_counter[instrAddr[11:2]]<=min_val;
else
    saturating_counter[instrAddr[11:2]]<=saturating_counter[instrAddr[11:2]]-1;
end

end

endmodule

但我收到了以下错误

%Warning-UNSIGNED: Bimodal.v:36: Comparison is constant due to unsigned arithmetic
%Warning-UNSIGNED: Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed /home/verilator-3.884/verilator_bin -O4 --cc MIPS.v --exe sim_main.cpp

我做错了吗？

Answer 1

您的编译器当前设置为在某些警告时失败。问题的根源可能是你的min_val参数当前是0.同时，你只检查min_val（除非你在某处覆盖参数，它总是为0）是否大于RHS上的2位值（右手边）没有任何迹象。这意味着它永远不会消极。

Is 0 > 0 ?  No
Is 0 > 1 ?  No
is 0 > 2 ?  No
Is 0 > 3 ?  No

答案总是不，所以每个警告的结果都是不变的。

你希望测试

Is 0 > 0 ? No
Is 0 > 1 ? No
Is 0 > -2 ? Yes
Is 0 > -1 ? Yes

如果需要，您需要更改逻辑类型，或更改比较。

Answer 2

请记住，verilog中的reg是无符号值，而无法为reg分配的是无符号值。并且您与零比较的所有未知值将大于或等于零。如果您想要签名比较，可以使用$signed()指令。

if(min_val>$signed(saturating_counter[instrAddr[11:2]]-1))

由于verilog与verilator的无符号算术错误，比较是恒定的

2 个答案: