如何让领先的活跃在vivado上

时间:2017-03-16 00:42:58

标签: verilog xilinx vivado

这个程序代表一个有限状态机,其中7段LED指向5计数。我需要将其设置为低电平而不是高电平但我不确定如何执行此操作。我也有测试平台。我知道最好为时钟使用always语句,但我可以稍后处理。

`timescale 1ns / 1ps

//inputs, outputs

module Counter(
    input u,
    input clrn,
    input clk,
    output reg a,
    output reg b,
    output reg c,
    output reg d,
    output reg e,
    output reg f,
    output reg g);

    reg [2:0] ns; //next state
    reg [2:0] q; //present state
//declaration of the states    
    parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

    always @ (posedge clk or negedge clrn)
    begin
    if(~clrn) //if reset present state q goes to 0
        q = S0;
    else
    begin
        case(q) //tests present state
            S0:
            if (u==1) begin
                ns = S1;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b0;
                g = 1'b0;
            end
            else begin
                ns = S5;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end

            S1:
            if (u==1) begin
                ns = S2;
                a = 1'b1;
                b = 1'b1;
                c = 1'b0;
                d = 1'b1;
                e = 1'b1;
                f = 1'b0;
                g = 1'b1;
            end
            else begin
                ns = S0;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b1;
                f = 1'b1;
                g = 1'b0;
            end

            S2:
            if (u==1) begin
                ns = S3;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b0;
                g = 1'b1;
            end
            else begin
                ns = S1;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b0;
                g = 1'b0;
            end            

            S3:
            if (u==1) begin
                ns = S4;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end
            else begin
                ns = S2;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end   

            S4:
            if (u==1) begin
                ns = S5;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end
            else begin
                ns = S3;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b0;
                g = 1'b1;
            end

            S5:
            if (u==1) begin
                ns = S0;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b1;
                f = 1'b1;
                g = 1'b0;
            end
            else begin
                ns = S4;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end

        endcase

        q = ns;

    end

    end

endmodule

TESTBENCH:

`timescale 1ns / 1ps

module testbench;

reg U, CLK, CLRN;
wire A, B, C, D, E, F, G;

Counter inst(

.clk (CLK),
.u (U),
.clrn (CLRN),
.a (A),
.b (B),
.c (C),
.d (D),
.e (E),
.f (F),
.g (G));

initial

begin //CLRN starts low, CLK starts high, U starts high

CLRN = 1'b0;

CLK = 1'b1;

U = 1'b1;

//CLK will change every ns

#1 CLRN = 1'b1;
CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0; //On the ns 17 u will change to low
U = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

end

endmodule

非常感谢!

1 个答案:

答案 0 :(得分:0)

最快捷的方法是简单地更改每个州的通行证分配。

在第一种情况下你有这个

            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;

将其更改为此,您将反转输出的极性。

            a = 1'b1; // old setting 1'b0;
            b = 1'b0; // old setting 1'b1;
            c = 1'b0; // old setting 1'b1;
            d = 1'b1; // old setting 1'b0;
            e = 1'b1; // old setting 1'b0;
            f = 1'b1; // old setting 1'b0;
            g = 1'b1; // old setting 1'b0;

或者,您可以制作新的寄存器

reg a_n, b_n, c_n, d_n, e_n, f_n, g_n;

然后完成所有寄存器分配并将它们更改为这些新的寄存器名称

a_n = 1'b0;
b_n = 1'b1;
c_n = 1'b1;
d_n = 1'b0;
e_n = 1'b0;
f_n = 1'b0;
g_n = 1'b0;

然后创建一个新的始终阻止

// Invert the register outputs 
always @ (a_n or b_n or c_n or d_n or e_n or f_n or g_n)
begin
    a <= ~a_n;
    b <= ~b_n;
    c <= ~c_n;
    d <= ~d_n;
    e <= ~e_n;
    f <= ~f_n;
    g <= ~g_n;
end