Question

我正在尝试创建一个7段LED计数器，我遇到的两个问题是在模拟波形中只显示为X，我不知道如何采取q这是当前状态并制作它波形到测试平台。我认为这就像在测试平台中创建称为Q2，Q1和Q0的导线，并添加它们 .q [2]（Q2）等等，但似乎并不喜欢。我对此非常新，所以它可能非常简单。谢谢！

`timescale 1ns / 1ps

//inputs, outputs

module Counter(
input u,
input clrn,
input clk,
output reg a,
output reg b,
output reg c,
output reg d,
output reg e,
output reg f,
output reg g);

reg [2:0] ns; //next state
reg [2:0] q; //present state
//declaration of the states    
parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

always @ (negedge clk or posedge clrn)
begin
if(clrn) //if reset present state q goes to 0
    q = S0;
else
begin
    case(q) //tests present state
        S0:
        if (u==1) begin
            ns = S1;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;
        end
        else begin
            ns = S5;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end

        S1:
        if (u==1) begin
            ns = S2;
            a = 1'b1;
            b = 1'b1;
            c = 1'b0;
            d = 1'b1;
            e = 1'b1;
            f = 1'b0;
            g = 1'b1;
        end
        else begin
            ns = S0;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b1;
            f = 1'b1;
            g = 1'b0;
        end

        S2:
        if (u==1) begin
            ns = S3;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b0;
            g = 1'b1;
        end
        else begin
            ns = S1;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;
        end            

        S3:
        if (u==1) begin
            ns = S4;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end
        else begin
            ns = S2;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end   

        S4:
        if (u==1) begin
            ns = S5;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end
        else begin
            ns = S3;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b0;
            g = 1'b1;
        end

        S5:
        if (u==1) begin
            ns = S0;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b1;
            f = 1'b1;
            g = 1'b0;
        end
        else begin
            ns = S4;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end

    endcase

    q = ns;

end

end

endmodule

测试平台：

`timescale 1ns / 1ps


module testbench;

reg U, CLK, CLRN;
wire A, B, C, D, E, F, G;

Counter inst(

.clk (CLK),
.u (U),
.clrn (CLRN),
.a (A),
.b (B),
.c (C),
.d (D),
.e (E),
.f (F),
.g (G));

initial

begin //CLRN starts low, CLK starts high, U starts high

CLRN = 1'b0;

CLK = 1'b1;

U = 1'b1;

//CLK will change every ns

#1 CLRN = 1'b1;
CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0; //On the ns 17 u will change to low
U = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

end

endmodule

Answer 1

请参考这些信号源向波形添加信号：

1- https://cseweb.ucsd.edu/classes/wi11/cse141L/tipsandtricks.html

2- https://forums.xilinx.com/t5/Simulation-and-Verification/Viewing-internal-signal-waveforms-in-ISIM/td-p/244736

3- ug937-vivado-design-suite-simulation-tutorial

另外考虑看Xilinx模板代码，我认为您的编码风格不是标准的。（模拟和状态机）

Answer 2

您需要调整两个主要问题。

你有一个CLRn，但你说if(clrn)。负极性复位需要if (~clrn)
您在always语句中的重置是在灵敏度列表中寻找正边缘过渡。你至少需要对clrn敏感，就像这样......

always @ (negedge clk or negedge clrn)

但我建议将以下内容作为更标准的正时钟边缘灵敏度......

always @ (posedge clk or negedge clrn)

vivado在输出中遇到X波形问题，采用数组并在7段led计数器有限状态机上进行波形

2 个答案: