qemu-system-riscv现在可以添加网络设备吗?

时间:2017-02-17 01:58:13

标签: qemu riscv

当我使用 public partial class LoginPage : ContentPage { public LoginPage() { InitializeComponent(); } async void LoginBtnClicked(object sender, EventArgs args) { await Navigation.PushModalAsync(new AuthenicationBrowser()); } public async void PopModal() { Debug.WriteLine("Navigation.ModalStack PopModal ===> {0}", App.Current.MainPage.Navigation.ModalStack.Count); await App.Current.MainPage.Navigation.PopModalAsync(); } } 时,我发现>>> from pathlib import Path >>> filename = Path('/some/path/somefile.txt') >>> filename_wo_ext = filename.with_suffix('') >>> filename_replace_ext = filename.with_suffix('.jpg') >>> print(filename) /some/path/somefile.ext >>> print(filename_wo_ext) /some/path/somefile >>> print(filename_replace_ext) /some/path/somefile.jpg 选项不起作用。这是否意味着qemu-system-riscv不支持添加网络设备?

1 个答案:

答案 0 :(得分:1)

是的,qemu-system-riscv仅支持HTIF控制台或SiFive UART,请检查https://github.com/riscv/riscv-qemu(您可以尝试定义其他控制台/ UART并启动旧的经典PPP over serial

  

Current limitations:

     

当前的RISC-V板定义仅提供HTIF控制台设备。已经从riscv-linux中删除了对其他基于HTIF的设备的支持;因此,QEMU也不再支持它们。

实际上,qemu中有两个所谓的“板”(虚拟机的定义,其内存和外围设备)用于RISC-V,两者都在这里:https://github.com/riscv/riscv-qemu/tree/master/hw/riscv

  • riscv-qemu/hw/riscv/riscv_board.c(“RISC-V Generic Board”,“Spike”):3个串行设备,带有复位的“rv64imafd”指令集的cpus,主RAM @ 0x80000000,引导ROM,虚拟IPI RAM @ 0x40001000,内核加载器,rtc时钟@ 0x40000000 + 8,htif寄存器在ELF中定义的地址。 “smp”已列出,但我不确定它是否已实施。插入某些网络设备没有任何标准总线;对于VirtIO设备,只有一行代码是注释/* TODO: VIRTIO */
 * This provides a RISC-V Board with the following devices:
 *
 * 0) HTIF Test Pass/Fail Reporting (no syscall proxy)
 * 1) HTIF Console
 *
 * These are created by htif_mm_init below.
 *
 * This board currently uses a hardcoded devicetree that indicates one hart.
  • riscv-qemu/hw/riscv/sifive_board.c(“SiFive U500 SDK兼容”):内核加载程序,“rv64imafd”的cpu,带有reset,RAM&引导ROM,虚拟IPI和PLIC内存,3个串行端口,config_string中的2个plic设备,rtc和uart(sifive_uart_create),定时器。完全相同的VIRTIO设备实现:/* TODO: VIRTIO */
 * This provides a RISC-V Board with the following devices:
 *
 * 0) UART comptible with that expected by the SiFive U500 SDK
 *
 * This board currently uses a hardcoded devicetree that indicates one hart.