如果然后进程,VHDL语法错误

时间:2017-01-10 11:16:15

标签: vhdl

library ieee;
use ieee.std_logic_1164.all;

entity basic_shift_register_with_multiple_taps is

    generic
    (
        DATA_WIDTH : natural := 8

    );

    port 
    (
        clk          : in std_logic;
        enable       : in std_logic;
        sr_one       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_two       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_out       : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
    );

end entity ;

architecture rtl of basic_shift_register_with_multiple_taps is


    signal sig_out  :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
    variable count  : integer := 0;
    variable count1 : integer := 0;

begin

    process (clk,enable,sr_one,sr_two,sig_out)

    begin

        if(enable = '0' or count = 16) then 
            count := 0;
            count1 := 0;
        else if (clk'event and clk='1') then
            sig_out(count) <= sr_one(count1);

            count := count + 1;

        else --if (clk'event and clk='0') then--
            sig_out(count) <= sr_two(count1);
            count := count + 1;

        end if;

        count1 := count1 + 1;   


(54)    end process;

    sr_out <= sig_out;

(58) end rtl;

错误:

  

错误(10500):teste.vhd(54)附近文本“process”的VHDL语法错误;期待“如果”

     

错误(10500):teste.vhd(58)附近文本“rtl”的VHDL语法错误;期待“如果”

1 个答案:

答案 0 :(得分:0)

你的问题是你的第二个if语句

if (clk'event and clk='1') then

没有end if与之关联。因此,当编译器到达第54行时,它会遇到end process之前遇到的end if。而不是这个

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else if (clk'event and clk='1') then
    sig_out(count) <= sr_one(count1);

    count := count + 1;

else --if (clk'event and clk='0') then--
    sig_out(count) <= sr_two(count1);
    count := count + 1;

end if;

这样做:

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else
    if (clk'event and clk='1') then
        sig_out(count) <= sr_one(count1);
        count := count + 1;
    else --if (clk'event and clk='0') then--
        sig_out(count) <= sr_two(count1);
        count := count + 1;
    end if;
end if;

但是,如果您打算合成这个,那么您的语法错误是您最不担心的。请参阅this answer