Vivado IP正在产生过多的Modelsim警告，这使得我很难评估我真正关心的警告的模拟。
我从Modelsim命令documentation看到，为了抑制警告，我需要包含参数-suppress，然后是警告编号。我目前的实施如下......
vsim -voptargs=+acc \
-L work \
-L xil_defaultlib \
-L secureip \
-L simprims_ver \
-L unifast_ver \
-L unimacro_ver \
-L unisims_ver \
-L xpm \
-L fifo_generator_v13_1_1 \
-L blk_mem_gen_v8_3_3 \
work.blr_tb xil_defaultlib.glbl -l sv_sim.log -suppress 3015,3017,3722
此代码段有效，但我担心这会抑制由我自己的rtl问题所造成的警告。有没有办法抑制IP的特定警告？
作为参考，警告全部来自Vivado MIG IP，看起来像这样......
# ** Warning: (vsim-3017) ../../ip/xc7k160t2ffg676-2/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v(1260): [TFMPC] - Too few port connections. Expected 9, found 8.
# Time: 0 fs Iteration: 0 Instance: /blr_tb/blr_sbk_top_i/ddr3_balor_i/u_mig_ddr3_64bit_32G/u_mig_ddr3_64bit_32G_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP/gen_dqs_iobuf[0]/gen_dqs_diff/u_iobuf_dqs File: C:/Xilinx/Vivado/2016.2/data/verilog/src/unisims/IOBUFDS_DIFF_OUT_DCIEN.v
使用以下命令编译MIG ...
vlog -work xil_defaultlib -incr \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/mig_ddr3_64bit_32G.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/mig_ddr3_64bit_32G_mig_sim.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/clocking/*.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/controller/*.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/ecc/*.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/ip_top/*.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/phy/*.v" \
"$SBK_IP_DIR/mig_ddr3_64bit_32G/mig_ddr3_64bit_32G/user_design/rtl/ui/*.v"