尝试模拟以下内容时，我收到了上述错误。
来源
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity AAM is
generic(
constant MEMORY_WIDTH : integer := 7;
constant MEMORY_SIZE : integer := 255
);
port(
CLOCK : in std_ulogic;
EVENT_DATA : out std_ulogic_vector( MEMORY_WIDTH downto 0 );
EVENT_ADDRESS : out std_ulogic_vector( MEMORY_WIDTH downto 0 );
READ_DATA : out std_ulogic_vector( MEMORY_WIDTH downto 0 );
READ_ADDRESS : in std_ulogic_vector( MEMORY_WIDTH downto 0 );
READ_STATUS : out std_ulogic;
WRITE_DATA : in std_ulogic_vector( MEMORY_WIDTH downto 0 );
WRITE_ADDRESS : in std_ulogic_vector( MEMORY_WIDTH downto 0 );
WRITE_STATUS : out std_ulogic
);
end AAM;
architecture dataflow of AAM is
subtype WORD is std_ulogic_vector( MEMORY_WIDTH downto 0 );
type CACHE is array ( MEMORY_SIZE downto 0 ) of WORD;
signal MEMORY : CACHE;
begin
process( CLOCK )
begin
if ( falling_edge(CLOCK) ) then
READ_DATA <= MEMORY( conv_integer( READ_ADDRESS ) );
READ_STATUS <= '1';
WRITE_STATUS <= '0';
else
MEMORY( conv_integer( WRITE_ADDRESS ) ) <= WRITE_DATA;
EVENT_DATA <= WRITE_DATA;
EVENT_ADDRESS <= WRITE_ADDRESS;
READ_STATUS <= '0';
WRITE_STATUS <= '1';
end if;
end process;
end dataflow;
构建
vasy -Vao design
genpat design
asimut -b design design design_out
输出
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design... BEH：正在编译design.vbe（行为）...design.vbe错误行3438：语法错误design.vbe错误18行3438：非法并发声明cannot continue further more. have a nice day...
到目前为止，联盟工具链一直是个蠢货，有人能指出我正确的方向吗？
注意：我没有包含design.c / pattern源，因为VBE文件失败并从第一阶段vasy -Vao design生成。然而，直到最后阶段才报告错误。