我正在尝试在Quartus II上为离散时间FIR滤波器实现一个测试平台。测试平台将从.txt文件中读取输入代码,并将输出写入另一个.txt文件。
单击RTL模拟按钮时,ModelSim上会出现以下错误:
错误:filter2 / simulation / modelsim / filter.vht(83):非法顺序语句。
错误:filter2 / simulation / modelsim / filter.vht(111):子程序“read”没有可行的条目。
错误:filter2 / simulation / modelsim / filter.vht(147):VHDL编译器退出
如何解决这些错误?我写的代码是:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_textio.all;
USE STD.TEXTIO.ALL;
USE ieee.std_logic_arith.all;
ENTITY filter_vhd_tst IS
END filter_vhd_tst;
ARCHITECTURE filter_arch OF filter_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL clk_enable : STD_LOGIC;
SIGNAL filter_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL filter_out : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
signal flag : std_LOGIC := '0';
COMPONENT filter
PORT (
clk : IN STD_LOGIC;
clk_enable : IN STD_LOGIC;
filter_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
filter_out : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
reset : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : filter
PORT MAP (
-- list connections between master ports and signals
clk => clk,
clk_enable => clk_enable,
filter_in => filter_in,
filter_out => filter_out,
reset => reset
);
init : PROCESS
-- variable declarations
--constant clk_period : time := 20ns;
BEGIN
-- code that executes only once
clk_enable <= '1';
reset <= '0';
clk <= '0';
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
clk_process:PROCESS
BEGIN
clk <= '0';
wait for 10 ns; --clk_period/2;
clk <= '1';
wait for 10 ns; --clk_period/2;
end process;
--Stimulus
stim:process
begin
wait for 100 ns;
wait for 2000 ns;--clk_period*100;
wait for 50 us;
--inserting stimulus
wait;
end process;
process(clk)
file in_file : text open READ_MODE is "wave.txt";
variable in_line : LINE;
variable filed : integer range 0 to 65535;
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '1')then
if(divider = 0)then
if NOT ENDFILE(in_file)then
READLINE(in_file, in_line);
READ(in_file, filed);
filter_in <= conv_std_logic_vector(filed,16);
else
flag <= '1';
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
process(clk)
file RESULT_FILE: text open WRITE_MODE is "out.txt";
variable outline : LINE;
variable temp : std_LOGIC_VECTOR(32 downto 0);
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '0')then
if(divider = 0)then
if(flag = '0')then
temp := filter_out;
write(outline, temp);
writeLine(RESULT_FILE, outline);
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
--WAIT;
END PROCESS always;
END filter_arch;
答案 0 :(得分:1)
第一个错误,第83行,是由于流程中的流程:
always : PROCESS
BEGIN
clk_process : PROCESS
由于进程声明不是顺序语句,因此会收到错误消息:
错误:filter2 / simulation / modelsim / filter.vht(83):非法顺序语句。
第二个错误是因为read
将line
作为第一个参数,但是给出了file
:
READ(in_file, filed);
所以改为:
READ(in_line, filed);