I'm designing a project for school, I'm required to make the code work with Verilog. The goal is to have 4 inputs (buttons on the FPGA), quarter, nickel, dime, and reset, as well as switches to identify what kind of burrito I want to purchase (Bean burrito, steak burrito, and chicken burrito). I need to display the current money inserted on a seven segment display. The problem I'm having is that the seven segment display is not working. It only displays my default, none of the switches work and neither do the buttons. I found this website looking for help, and discovered other examples, I tried following some of them but I'm still stuck. I would appreciate the help, this is my first time coding period. I couldn't insert the entire code for some reason, so I put the main parts. I think the beginning is whats wrong.
module LabX(quarter, nickel, dime, BB, CB, SB, clk, reset, current_state, R, L, next_state, give_BB, give_CB, give_SB, Rssd, Lssd, ld);
input quarter, nickel, dime, BB, CB, SB, clk, reset, R, L;
output next_state, give_BB, give_CB, give_SB;
output [6:0] Rssd, Lssd, current_state;
output [2:0] ld;
reg [6:0] current_state, next_state, give_BB, give_CB, give_SB, Rssd, Lssd, ld;
parameter cent0 = 0, cent5= 1, cent10 = 2, cent15=3, cent20 =4, cent25 =5, cent30=6, cent35=7, cent40=8, cent45=9, cent50=10, cent55=11, cent60=12, cent65=13, cent70=14, cent75=15, cent80=16, cent85=17, cent90=18, cent95=19, cent100=20;
always @(posedge clk or posedge reset)
begin
if(reset)
current_state = cent0;
else
current_state = next_state;
end
always @(nickel or dime or quarter or BB or CB or SB or reset)
begin
case(current_state)
cent0: begin
if(nickel)
next_state = cent5;
else if(dime)
next_state = cent10;
else if(quarter)
next_state = cent25;
else if(reset)
next_state = cent0;
end
I continued this process and to show when you have enough to purchase I entered this...
cent55: begin
if(nickel)
next_state = cent60;
else if(dime)
next_state = cent65;
else if(quarter)
next_state = cent80;
else if(reset)
next_state = cent0;
if(BB)
give_BB = 1;
else if(CB)
give_CB = 1;
else if(SB)
give_SB = 0;
end
For the Seven segment display I entered the code as follows:
case (current_state)
cent0:Rssd=7'b1111110;
cent5:Rssd=7'b1011011;
cent10:Rssd=7'b1111110;
cent15:Rssd=7'b1011011;
cent20:Rssd=7'b1111110;
cent25:Rssd=7'b1011011;
cent30:Rssd=7'b1111110;
cent35:Rssd=7'b1011011;
cent40:Rssd=7'b1111110;
cent45:Rssd=7'b1011011;
cent50:Rssd=7'b1111110;
cent55:Rssd=7'b1011011;
cent60:Rssd=7'b1111110;
cent65:Rssd=7'b1011011;
cent70:Rssd=7'b1111110;
cent75:Rssd=7'b1011011;
cent80:Rssd=7'b1111110;
cent85:Rssd=7'b1011011;
cent90:Rssd=7'b1111110;
cent95:Rssd=7'b1011011;
cent100:Rssd=7'b1111110;
BB:Rssd=7'b0011111;
CB:Rssd=7'b0011111;
SB:Rssd=7'b0011111;
default: Rssd = 7'b1111110;
endcase
end
endmodule
I did this for Lssd as well. I believe the UCF file is correct, something is wrong with my code.