1-下面的Verilog是否会合成(在Altera的Quartus中)到连接到一根线的1024个三态器件的总线? 2-它比1024或门的二叉树更快(时钟延迟)吗?
module TriBus #(parameter N = 1024)(inb, enb, outb);
input inb, enb;
output outb;
wire [N:1]inb;
wire [N:1]enb;
wire outb;
wire [N:1] orbus;
genvar I;
generate
for (I=1; I<N; I=I+1)
begin
assign outb = (enb[I])? inb[I] : 1'bz;
end
endgenerate
endmodule