我正在编写一个Verilog代码，以通过uart从fpga max10向PC发送1000个字节。我将数据写入Ip目录FIfo，然后读取并将其发送到UART线。我的问题是状态机停留在一个状态且不会改变。
以下是高级代码：
module XPM123(
input clk_25_max10,
input clk_50_max10,
input fpga_resetn,
input [3:0] user_pb,
output uart_tx
);
wire TX_DV;
wire Fifo_wr_en;
wire Fifo_rd_en;
wire [7:0]data_in;
wire [7:0]data_out;
wire full_flg;
wire empty_flg;
wire [7:0] TX_Byte;
wire Packet_Valid;
reg start;
reg reset_variables;
reg [2:0] start_delay;
reg rising_edge_start;
reg Next_Line_delay1;
wire Next_Line;
wire Flush_Fifo;
wire txclk_en;
wire rxclk_en;
always @ (posedge clk_25_max10 or negedge user_pb[1]) begin
if(!user_pb[1])
begin
start <= 1'b0;
end
else
begin
start <= 1'b1;
end
end
Write_Packet_To_Fifo inst_Write_Packet_To_Fifo
(
.i_Clock(clk_25_max10),
.i_TX_Done(TX_Done),
.i_Tx_Active(TX_Active),
.User_Start(start),
.Fifo_full_flg(full_flg),
.Fifo_empty_flg(empty_flg),
.Fifo_Data_Out(data_out),
.i_reset(!fpga_resetn),
// .o_Packet_Valid(Packet_Valid),
.Fifo_wr_en(Fifo_wr_en),
.Fifo_rd_en(Fifo_rd_en),
.data_in(data_in),
.Flush_Fifo(Flush_Fifo),
.o_TX_Byte(TX_Byte),
.o_TX_DV(TX_DV),
//.o_Next_Line(Next_Line)
);
FIFO FIFO_inst (
.aclr (Flush_Fifo ),
.clock (clk_25_max10),
.data ( data_in),
.rdreq (Fifo_rd_en),
.wrreq (Fifo_wr_en ),
.empty ( empty_flg ),
.full ( full_flg ),
.q ( data_out ),
.usedw ( usedw_flg )
);
transmitter inst_transmitter(
.din(TX-Byte),
.wr_en(TX-DV),
.clk_50m(clk_25_max10),
.clken(txclk_en),
.tx(uart_tx),
.tx_busy(TX_Active),
.tx_done(TX_Done)
);
baud_rate_gen inst_baud_rate_gen(
.clk_50m(clk_25_max10),
.rxclk_en(rxclk_en),
.txclk_en(txclk_en)
);
endmodule
这是我的fsm的代码
module Write_Packet_To_Fifo(
input i_Clock,
input i_TX_Done,
input User_Start,
input Fifo_full_flg,
input Fifo_empty_flg,
input [7:0]Fifo_Data_Out,
input i_Tx_Active,
input i_reset,
// output reg o_Packet_Valid,
output reg Fifo_wr_en,
output reg Fifo_rd_en,
output reg [7:0]data_in,
output reg [7:0] o_TX_Byte,
output reg Flush_Fifo,
output reg o_TX_DV
// output reg o_Next_Line
);
parameter Initial = 0, Write_Data_Fifo = 1, Read_Valid_Data = 2, Wait_for_Tx_done =3;
reg[2:0]state;
reg [9:0] Fifo_count;
reg [7:0] F_Count;
always @(posedge i_Clock)
begin
case(state)
Initial:
begin
// o_Next_Line <=0;
F_Count <=0;
Fifo_count<=0;
Flush_Fifo <=1;
//o_Packet_Valid <=0;
Fifo_rd_en <=0;
Fifo_wr_en <=0;
o_TX_DV <=0;
if(User_Start == 1)
begin
state <= Initial;
end
else
begin
Flush_Fifo <=0;
state <= Write_Data_Fifo;
end
end
Write_Data_Fifo:
begin
// o_Next_Line <=0;
o_TX_DV <=0;
Fifo_wr_en <=1;
if(Fifo_count > 1000)
begin
Fifo_wr_en <=0;
state <= Read_Valid_Data;
Fifo_count <=0;
F_Count<=0;
end
else
begin
state <= Write_Data_Fifo;
if(F_Count== 250)
begin
F_Count <= 0;
end
else
begin
data_in <= F_Count;
F_Count <= F_Count + 1;
Fifo_count <= Fifo_count + 1;
end
end
end
Read_Valid_Data:
begin
// o_Next_Line <=0;
// if(!i_Tx_Active)
// begin
Fifo_rd_en <=1;
o_TX_Byte <= Fifo_Data_Out;
o_TX_DV <=1;
state <= Wait_for_Tx_done;
// end
// else
// begin
// state <= Read_Valid_Data;
// end
end
Wait_for_Tx_done:
begin
o_TX_DV <=0;
Fifo_rd_en <=0;
// o_Next_Line <=0;
if(i_TX_Done)
begin
//state <= Line_Finished;
if(!Fifo_empty_flg)
begin
state <= Read_Valid_Data;
end
else
begin
Fifo_rd_en <=0;
state <= Initial;
end
end
else
begin
state <= Wait_for_Tx_done;
end
end
/* Line_Finished:
begin
o_Next_Line <= 1'b1;
o_TX_DV <=0;
if(!Fifo_empty_flg)
begin
state <= Read_Valid_Data;
end
else
begin
Fifo_rd_en <=0;
state <= Initial;
end
end*/
default :
state <= Initial;
endcase
end
endmodule
还有另外一个关于uart的文件，但我认为它不会影响我的问题，但是无论如何都在这里
module transmitter(input wire [7:0] din,
input wire wr_en,
input wire clk_50m,
input wire clken,
output reg tx_done,
output reg tx,
output wire tx_busy);
initial begin
tx = 1'b1;
end
parameter STATE_IDLE = 2'b00;
parameter STATE_START = 2'b01;
parameter STATE_DATA = 2'b10;
parameter STATE_STOP = 2'b11;
reg [7:0] data = 8'h00;
reg [2:0] bitpos = 3'h0;
reg [1:0] state = STATE_IDLE;
always @(posedge clk_50m) begin
case (state)
STATE_IDLE: begin
tx_done <=0;
if (wr_en) begin
state <= STATE_START;
data <= din;
bitpos <= 3'h0;
end
end
STATE_START: begin
tx_done <=0;
if (clken) begin
tx <= 1'b0;
state <= STATE_DATA;
end
end
STATE_DATA: begin
tx_done <=0;
if (clken) begin
if (bitpos == 3'h7)
state <= STATE_STOP;
else
bitpos <= bitpos + 3'h1;
tx <= data[bitpos];
end
end
STATE_STOP: begin
if (clken) begin
tx <= 1'b1;
tx_done <=1;
state <= STATE_IDLE;
end
end
default: begin
tx <= 1'b1;
state <= STATE_IDLE;
end
endcase
end
assign tx_busy = (state != STATE_IDLE);
endmodule
我使用了信号选项卡，该选项卡在单击按钮（User-pb [1]）时触发， 默认情况下，Wait_for_tx-done状态为高，情况并非如此。任何指导都会有所帮助