Question

所以我在verilog中设计一个ALU，而我正在学习它。我想出了以下代码：测试平台：

module ALUtb;

reg clock = 1'b0;

reg [0:7] val1;
reg [0:7] val2;

initial begin
val1 = 8'b01010100;
val2 = 8'b10101000;

#50 $finish;

 end
 ALU piet(val1, val2,, clock);

always begin
  #5 clock = ~clock
;
end

  endmodule

 Main code:

 // Code your design here

     module ALU(
     a1, a2, out, clock
     );

  output [0:7] out;
  input [0:7] a1;
  input [0:7] a2;
  input clock;

  wire clock;
  reg  out;
  wire co;
  wire a1, a2;

   wire [0:7] poep;

   initial begin
     $monitor("Out=%d, co=%d, a=%d, a2=%d, poep=%d, clock=%d", out, co, a1,   a2,     poep, clock);

  end

  always @ (posedge clock) begin

     out <= poep;

   end

  adder addy(.output_byte(poep), .co(co), .a1(a1), .a2(a2), .clock(clock));

endmodule 

 module adder(
   output_byte, co, a1, a2, clock
  );
  initial begin
    output_byte = 8'b00000011;
  end
  input [0:7] a1;
  input [0:7] a2;
  input clock;

  output [0:7] output_byte;
  output output_bit;

  output co;

  wire c1;
  reg b1, b2;
  reg [0:7] output_byte;
  wire output_bit;

  integer i;

  always @ (posedge clock) begin
     for(i = 0; i < 8; i = i + 1) begin

      b1 = (a1[i] & (1 << i));
      b2 = (a2[i] & (1 << i));  

      #1 output_byte[i] = output_bit;
  end
  end

 bitadder b_adder(.out(output_bit), .co(), .a1(b1), .a2(b2), .c1(c1));

endmodule

 // Deze module is een 1-bits adder. 
 module bitadder(out, co, a1, a2, c1);

  output out, co;
  input a1, a2, c1;

  wire out, co;

  wire a1;
  wire a2;
  wire c1;

  assign {co, out} = a1 + a2 + c1;

endmodule

所以在输出中我得到了：

Out=  x, co=z, a= 84, a2=168, poep=  3, clock=0
Out=  3, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  3, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0

正如您所看到的，这只是一个8位加法器。因为即使这还没有奏效，我们还没有进行。我的具体问题是：为什么输出没有正确变化？ Poep就像是实际输出的缓冲区。 co是进位，a是第一个数字，a2是第二个数字，c1是进位，其余的应该说明一切。为什么我的输出未定义？

非常感谢任何帮助！

提前致谢！

Answer 1

好吧，因为您在每个时钟周期将其分配给值未定义的线路。如果你想让poep成为一个缓冲区，那就让它注册，而不是连线。电线没有保存数据。

我的ALU在verilog中的困难

1 个答案: