我对VHDL相对较新,所以我事先道歉,这个问题的解决方案对大多数人来说可能显得非常明显。在这段代码中,我试图模拟一个4位纹波进位加法器。但是,当我检查代码的语法时,我遇到了一些与类型不匹配有关的错误。
相关守则:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity toplevel is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
sum : out STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
count : out STD_LOGIC);
end toplevel;
40: architecture Structure of toplevel is
signal c1, c2, c3 : STD_LOGIC;
component mytutorial02
Port(
x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
count : out STD_LOGIC);
end component;
begin
54: Stage0: mytutorial02 port map(x=>x(0), y=>(0), cin=>cin, sum=>sum(0), count=>c1);
55: Stage1: mytutorial02 port map(x=>x(1), y=>(1), cin=>c1, sum=>sum(1), count=>c2);
56: Stage2: mytutorial02 port map(x=>x(2), y=>(2), cin=>c2, sum=>sum(2), count=>c3);
57: Stage3: mytutorial02 port map(x=>x(3), y=>(3), cin=>c3, sum=>sum(3), count=>count);
end Structure;
&安培;
entity mytutorial02 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
count : out STD_LOGIC);
end mytutorial02;
architecture Behavioral of mytutorial02 is
begin
sum <= (x xor y xor cin);
count <= (cin and x) or (x and y) or (cin and y);
end Behavioral;
具体错误是:
错误:HDLC编译器:839 - &#34; M:/ece230/tutorial02/toplevel.vhd"第54行: 类型std_logic与整数文字
不匹配错误:HDLC编译器:839 - &#34; M:/ece230/tutorial02/toplevel.vhd"第55行: 类型std_logic与整数文字
不匹配错误:HDLC编译器:839 - &#34; M:/ece230/tutorial02/toplevel.vhd"第56行: 类型std_logic与整数文字
不匹配错误:HDLC编译器:839 - &#34; M:/ece230/tutorial02/toplevel.vhd"第57行: 类型std_logic与整数文字
不匹配错误:HDLC编译器:854 - &#34; M:/ece230/tutorial02/toplevel.vhd"第40行: 由于先前的错误,单元被忽略。 VHDL文件
任何人都可以提供快速建议/见解如何解决这个问题?我试图自己排除故障,但无法确定问题所在。在我看来,所有变量都列为STD_LOGIC ......?
提前致谢。