Question

所以我一直在遵循EmbeddedMicro提供的关于使用HDL Lucid生成一个简单的16位CPU的指南。我的目标是将其转换为Quartus II中的Verilog。我遇到的问题是尝试将为我的数据目的地分配的位存储到指定寄存器内的特定位范围内。我遇到的第二个问题是使用全局常量作为案例值之一。我只需用常数值替换就可以解决这个问题。我已经将include文件添加到项目设置中。我仍然是Verilog的新手，所以他们的代码可能很多。

收到的错误在第57行

    shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register

错误读数：Verilog语法错误，接近文本：＆＃34; =＆＃34;。检查并修复在指定关键字

之前或之前出现的任何语法错误

`include "CPU_8/my_incl.vh"


module CPU(CLK,RST,WRITE,READ,ADDRESS,DOUT,DIN);
input RST,CLK;
input [0:7] DIN; //DATA in
output reg [0:7] ADDRESS;
output reg [0:7] DOUT; //DATA OUT
output reg WRITE,READ;

reg [0:15] INST;



//I am not sure if i set up the array for my registers correctly either
shiftreg shift_r[0:15] (RST, CLK, D, Q); //initialize shift_r and create array of 16 registers.
//Implicit net is created for the D and Q above when generating block file 

instRom_16 instRoms(ADDRESS, INST); //intialize InstRom_16 module



reg [0:3]OP;        // opcode
reg [0:3]ARG1;      // first arg
reg [0:3]ARG2;      // second arg
reg [0:3]DEST;      // destination arg
reg [0:7]CONSTANT;  //Constant



always@(posedge CLK)
begin
    WRITE = 0;      // don't write
    READ  = 0;       // don't read
    ADDRESS = 8'b0; // don't care
    DOUT = 8'b0;    // don't care

    instRoms.ADDRESS = shift_r.D[0]; //Set shift_reg to be program counter
    shift_r.D = shift_r.Q[0] + 1;   //increment program counter.




    OP = instRoms.INST[15:12]; // opcode first 4 bits
    DEST = instRoms.INST[11:8]; // destination one 4 bits
    ARG1 = instRoms.INST[7:4]; // argument2 is next 4 bits
    ARG2 = instRoms.INST[3:0];  // ARGUMENT2 is last 4 bits
    CONSTANT = instRoms.INST[7:0];

    //PERFORM OPERATIONS
        case (OP)
            4'd1: //tried to use `LOAD but that wouldn't point to the value in my include file
                READ = 1;                                 // request a read

                //line that is failing
                shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register

         //4'd2:


    endcase

    end


endmodule

这是我的包含文件

`ifndef _my_incl_vh_
`define _my_incl_vh_

`define NOP   = 4'd0;  // 0 filled

`define LOAD  = 4'd1; // load

`endif

Answer 1

你犯了一个小错误： shiftreg shift_r [0:15]（RST，CLK，D，Q）;

实例化一个shift_r数组，每个实例都有一个RST，CLK，D和Q.

所以shift_r.D [DEST}应该变为shift_r [DEST] .D和shift_r.Q [0]应该变为shift_r [0] .Q。

对于shift_r.D，猜猜你想要一个0:15的向量。您将需要使用例如15位将所有16位分配给15位的中间线。一个for循环。

希望这有帮助

Verilog：将位存储到初始化模块的特定位范围内

1 个答案: