Question

是否有办法根据参数操作变量实例化？

例如，如果我只放bit [WIDTH-1:0] a;并设置DEPTH == 1，那么WIDTH将为0而bit [-1:0] a;没有意义。

当我在下面的示例中对其进行编码时，我在第二个$ display上出现错误：＆＃34; Undeclared标识符：a＆＃34;。有没有办法在Verilog / SV中实现这一点，或者我的代码中是否有错误？

module test #(
  parameter DEPTH = 2,
  parameter WIDTH = $clog2(DEPTH)
)();

  generate
    if (WIDTH == 0) begin
      bit             a;
    end else begin
      bit [WIDTH-1:0] a;
    end
  endgenerate

  initial begin
    $display("WIDTH: %d", WIDTH);
    $display("Bit width of a: %d", $bits(a));
  end
endmodule: test

Answer 1

您需要做的就是

bit [(WIDTH>0 ? WIDTH-1 : 0):0] a;

Answer 2

Which version of Verilog are you using? $clog2 was introduced in Verilog-2005. Prior implementations, can give odd results.

See below, I did a loop to show incrementing depth versus result of clog2.

CLOG2(0) =           0
CLOG2(1) =           0
CLOG2(2) =           1
CLOG2(3) =           2
CLOG2(4) =           2

To represent the value of 1, for instance, you need 1 bit, not 0 To represent the value of 2, you need 2 bits...not 1. To represent the value of 4, you need 3 bits. CLOG2 is always 1 short at the transition points. The prior solution will not account for that as you grow.

So if you say

WIDTH = $clog(DEPTH+1);

I think you will automatically get the results you want.

Answer 3

我定期制作并使用它。它确定整数值的位宽度。特殊情况下为0将返回值1（您仍需要1位来保存该值）。假设您需要基于具有256个地址的内存定义索引变量

参数NUM_ADDR 256

localparam A_SZ = bit_size（NUM_ADDR-1）; //示例：255（最高地址）应返回8

逻辑[A_SZ-1：0]索引； //示例：[7：0]索引

然后我只需要更改NUM_ADDR

function integer bit_size;
input integer value;
reg [31:0] shifted;
integer res;
begin
  if (value != 0)
  begin
       shifted = value;
       for (res=0; (shifted != 0); res=res+1)
           shifted = shifted >> 1;
       bit_size = res;
  end
  else
     bit_size = 1; // minimum size, even for a value of 0
end
endfunction

Verilog / SV条件变量定义

3 个答案: