Question

我正在为一个16位数字实现一个重复的位移位器。要做到这一点，我有一个计数器，计算当我达到4'b1111时我移动和重置的次数。然后我有一个assign语句，它将MSB提供给输出。但是，逻辑使得输出每次都跳过第一个MSB。 在发生任何转变之前，包含第一个MSB的最简洁方法是什么？

CODE

module DAC_Control(
  input [15:0]data_in,
  input clk,
  input rst,
  output data_out,
  output reg cs,
  output reg enable
  );

//bit counter
  reg [3:0] bit_counter;

//to help with shifting
  reg [15:0] shifter;

  always @(data_in)
    shifter <= data_in;

//shifter
  always @(posedge (clk)) begin
    if (rst) begin
      bit_counter <= 4'b0;
      enable <= 1'b0;
      cs <= 1'b1;
      end
    else if (bit_counter == 4'b1111) begin
      bit_counter <= 4'b0;
      enable <= 1'b1;
      cs <= 1'b1;
    end
    else begin //this is the problem area
      bit_counter <= bit_counter + 1'b1;
      enable <= 1'b0;
      cs <= 1'b0;
      shifter <= shifter << 1;

    end
  end

  assign data_out = shifter[15];

endmodule

Answer 1

首先，有一个触发器来捕获data_in会更好。如果不是那么 in simulation ，如果data_in在移位之间发生变化，它将更新移位器并导致预期输出发生变化。最好基于合格事件（例如，下面示例中的counter_enable）捕获data_in。综合会产生错误，因为shifter有两个驱动程序。一个是连续分配shifter <= data_in;，另一个是转移逻辑shifter <= shifter << 1;

更新的示例代码应序列化数据。

module DAC_Control(
  input [15:0]data_in,
  input  counter_enable,
  input clk,
  input rst,
  output data_out,
  output reg cs,
  output reg enable
  );

//bit counter
  reg [3:0] bit_counter;

//to help with shifting
  reg [15:0] shifter;

//shifter
  always @(posedge (clk)) begin
    if (rst) begin
      bit_counter <= 4'b0;
      shifter <= 0;
      end
    else if (counter_enable == 1) begin
        shifter <= data_in;
        bit_counter <= 4'b0;
    end
    else begin
      shifter <= shifter << 1; // shifting 
      bit_counter <= bit_counter + 1'b1; // counter 
    end
  end

  always @(posedge (clk)) begin
    if (rst) begin
      enable <= 1'b0;
      cs <= 1'b1;
      end
    else if (bit_counter == 4'b1111) begin
      enable <= 1'b1;
      cs <= 1'b1;
    end
    else begin 
      enable <= 1'b0; // generate enable signals 
      cs <= 1'b0;
    end
  end

  assign data_out = shifter[15];

endmodule

如何从零计数器verilog

1 个答案: