如何启动有条件的计数器?

时间:2015-06-26 09:02:42

标签: asynchronous counter verilog

我正在尝试使用条件启动计数器(0到9),例如当条件发生时,计数器自行重置并开始计数直到10,然后从0开始。但它不起作用。

我已经拥有的是:

always @(posedge clk ) begin
  if (enable  & sample)
    counter <= 4'b0;
  else 
    counter <= counter + 4'b1;

  if ( counter == 4'd9 )
    counter <= 4'b0;
  else 
    counter <= counter + 4'b1;
end 

任何帮助?

1 个答案:

答案 0 :(得分:0)

It looks like 'enable and sample' clear, other wise it increments. Also in your example the comparison to 9 overrides the previous value, this check will reset to 0 or increment. You need to put this condition inside the else.

always @(posedge clk ) begin
  if (enable & sample) begin
    counter <= 4'b0;
  end
  else begin
    if ( counter == 4'd9 ) begin
       counter <= 4'b0;
    end
    else begin
      counter <= counter + 4'b1;
    end
  end
end

I suspect that you actually do not want it to increment when enable is low? which means the initial synch reset logic needs to be updated.