Question

我正在尝试将此代码实现到一个程序中，该程序将信号的脉冲宽度显示在basys2板上的七段显示器上，但是当我将代码下载到电路板上时，它只显示＆＃34; 0001＆＃34;我发现它只是从＆＃34; x＆lt; = a_count_pw + 1＆＃34;的部分显示1。它看起来只是添加1，即使没有输入信号也是如此。我也收到了这个警告＆＃34;信号不完整。信号不会在设计中驱动任何负载引脚。＆＃34;这应该是我的输入信号？这是我的代码。非常感谢任何帮助。谢谢。

顶级模块：main_top - Behaviral（main_top.vhd）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main_top is
port(
        J3_IO1 : in std_logic;
        mclk : in STD_LOGIC;
        btn : in STD_LOGIC_VECTOR(3 downto 0);
        a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
        an : out STD_LOGIC_VECTOR(3 downto 0);
        dp : out STD_LOGIC
     );
end main_top;

architecture Behaviral of main_top is
signal a_count_rst: STD_LOGIC;
signal a_count_pw: STD_LOGIC_VECTOR(15 downto 0);
signal a_count_pw_reported: STD_LOGIC_VECTOR(15 downto 0);
signal J3_IO1_q : STD_LOGIC;
signal J3_IO1_qq : STD_LOGIC;

component main
port(
    x : in STD_LOGIC_VECTOR(15 downto 0);
    clk : in STD_LOGIC;
    clr : in STD_LOGIC;
    a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
    an : out STD_LOGIC_VECTOR (3 downto 0);
    dp : out STD_LOGIC 
);
end component;


signal x: STD_LOGIC_VECTOR (15 downto 0);
begin

process(mclk)
 if mclk'event and mclk='1' then 
-- Synchronous process, clock edge is outer "if"
  if a_count_rst='1' then --synchronous reset
   a_count_pw <= b"0000000000000000";
   a_count_pw_reported <= a_count_pw_reported; 

  else
   J3_IO1_q <= J3_IO1;  -- First D FF stage 
   J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
  if  J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
      a_count_pw <= b"0000000000000000"; -- Start from 0 at rising edge
  elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
     a_count_pw_reported <= a_count_pw;  -- Capture count
   else
     x <= a_count_pw + 1;
   end if;
  end if;
 end if;
end process;


X1 : main port map
        (x=>x, clk=>mclk, clr=>btn(3), a_to_g=>a_to_g, an=>an, dp=>dp);


end Behaviral;

这是多路复用显示器的下一个模块。

模块：X1 - 主要 - 行为病毒（main.vhd）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main is
    port(
    x : in STD_LOGIC_VECTOR(15 downto 0);
    clk : in STD_LOGIC;
    clr : in STD_LOGIC;
    a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
    an : out STD_LOGIC_VECTOR (3 downto 0);
    dp : out STD_LOGIC;
    btn : in STD_LOGIC_VECTOR(3 downto 0);
    J3_IO1 : in STD_LOGIC;
    a_count_pw : in STD_LOGIC_VECTOR(15 downto 0)
);
end main;

architecture Behaviral of main is
signal s : STD_LOGIC_VECTOR (1 downto 0);
signal aen : STD_LOGIC_VECTOR (3 downto 0);
signal clkdiv : STD_LOGIC_VECTOR (20 downto 0);
signal digit : STD_LOGIC_VECTOR (3 downto 0);



begin
s <= clkdiv(18 downto 17);
aen <= "1111";
dp <= '1';


--4 to 1 multiplex
process(s, x)
begin
    case s is
    when "00" => digit <= x(3 downto 0);
    when "01" => digit <= x(7 downto 4);
    when "10" => digit <= x(11 downto 8);
    when others => digit <= x(15 downto 12);
    end case;
end process;


process(digit)
begin
    case digit is
        when X"0" => a_to_g <= "1000000"; --0
        when X"1" => a_to_g <= "1111001"; --1
        when X"2" => a_to_g <= "0100100"; --2
        when X"3" => a_to_g <= "0110000"; --3
        when X"4" => a_to_g <= "0011001"; --4
        when X"5" => a_to_g <= "0010010"; --5
        when X"6" => a_to_g <= "0000010"; --6
        when X"7" => a_to_g <= "1011000"; --7
        when X"8" => a_to_g <= "0000000"; --8
        when X"9" => a_to_g <= "0010000"; --9
        when X"A" => a_to_g <= "0001000"; --A
        when X"B" => a_to_g <= "0000011"; --b
        when X"C" => a_to_g <= "1000110"; --C
        when X"D" => a_to_g <= "0100001"; --d
        when X"E" => a_to_g <= "0000110"; --E
        when others => a_to_g <= "0001110"; --F
    end case;
end process;

--digit control
process(s, aen)
begin
    an <= "1111";
    if aen(conv_integer(s)) = '1' then
        an(conv_integer(s)) <= '0';
    end if;
end process;

--clock divider
process(clk, clr)
begin
    if clr ='1' then
        clkdiv <= (others => '0');
    elsif clk'event and clk = '1' then
        clkdiv <= clkdiv +1;
    end if;
end process;

end Behaviral;

这是我的ucf文件 ports.ucf

NET "mclk" LOC = "B8";

NET "a_to_g<0>" LOC = "L14";
NET "a_to_g<1>" LOC = "H12";
NET "a_to_g<2>" LOC = "N14";
NET "a_to_g<3>" LOC = "N11";
NET "a_to_g<4>" LOC = "P12";
NET "a_to_g<5>" LOC = "L13";
NET "a_to_g<6>" LOC = "M12";
NET "dp" LOC = "N13";

NET "an<3>" LOC = "K14";
NET "an<2>" LOC = "M13";
NET "an<1>" LOC = "J12";
NET "an<0>" LOC = "F12";

NET "btn<3>" LOC = "A7";


NET "J3_IO1" LOC = "J3";

Answer 1

在我看来，你没有绑定一些端口元素。我没有看到你用作信号宽度指示器的x。如果你看一下错误 - “信号不会驱动设计中的任何负载引脚”，这也很有意义。来自端口的元素应全部绑定到实际引脚。您可以将x视为16位宽的并行接口，您可以在其中读取输入值，然后将其用于您的原因。在我看来，你可以只使用x作为信号甚至变量，然后发回你应写入七段显示的实际字节

如何在vhdl中显示信号的脉冲宽度？

1 个答案: