Question

我正在尝试用verilog编写代码并在设计愿景中将其合成，但在详细阐述设计愿景时会给出以下错误：

net“countS [5]”由多个来源驱动，至少有一个来源是常数净 net“countS [4]”由多个源驱动，并且至少一个源是恒定的净

net“countS [3]”由多个来源驱动，并且至少有一个来源是常数净 net“countS [2]”由多个源驱动，并且至少有一个源是恒定网络 net“countS [1]”由多个源驱动，并且至少一个源是恒定网络 net“countS [0]”由多个源驱动，并且至少一个源是恒定网络 net“countH [5]”由多个源驱动，并且至少一个源是恒定网络 net“countH [4]”由多个源驱动，并且至少有一个源是恒定网络 net“countH [3]”由多个来源驱动，并且至少有一个来源是恒定净值 net“countH [2]”由多个源驱动，并且至少有一个源是恒定网络 net“countH [1]”由多个源驱动，并且至少有一个源是恒定网络 net“countH [0]”由多个来源驱动，至少有一个来源是常数净

我的代码存在于下面：

module main(clk,ts1,ts2,ts3,ts4,mode,res);
//clock of circuit
input clk;

//input switchs that indicate delays in test mode
input [3:0] ts1;
input [3:0] ts2;
input [3:0] ts3;
input [3:0] ts4;

//input switch that indicate mode of circuit
input [1:0] mode;

//output that indicate state of circuit
output reg [2:0] res;

//regs for counting
reg [5:0] countH;
reg [5:0] countS;

//array that indicate delays
reg [7:0] delays [3:0];

initial begin
    //resetting circuit variables
    countH = 0;
    countS = 0;
    res = 0;

    //setting delays for regular mode
    delays[0] = 30; //rg
    delays[1] = 5;  //ry
    delays[2] = 45; //gr
    delays[3] = 5;  //yr
end


//trig always whenever mode was changed
always @(mode[0] or mode[1]) begin
    //restarting timer
    countH = 0;
    countS = 0;
    //mean that mode is regular
    if(mode == 2'b00) begin
        delays[0] = 30; //rg
        delays[1] = 5;  //ry
        delays[2] = 45; //gr
        delays[3] = 5;  //yr
    //mean that mode is test mode
    end else if(mode == 2'b01) begin
        //setting delays according to input switchs
        delays[0] = ts1;    //rg
        delays[1] = ts2;    //ry
        delays[2] = ts3;    //gr
        delays[3] = ts4;    //yr
    //mean that mode is standby
    end else begin
        delays[0] = 0;  //rg
        delays[1] = 0;  //ry
        delays[2] = 0;  //gr
        delays[3] = 0;  //yr
        res = 4;
    end
end

//trig in all clocks
always @(negedge clk) begin
    countH = countH + 1;
    //count=60 mean 1sec
    if(countH == 60) begin
        //updating variables
        countH = 0;
        countS = countS + 1;

        //mean that mode is standby
        if(mode == 2) begin
            res = 4;
            countS = 0;
        //mean that mode is regular or test
        end else begin
            //checking for delay
            if(countS == delays[res]) begin
                countS = 0;
                res = res + 1;
                if(res == 4) begin
                    res = 0;
                end
            end
        end
    end
end
endmodule

Answer 1

错误由综合工具生成，因为综合试图将写入i Verilog的设计转换为硬件，但在此转换期间，它发现导线countS（和其他）是从多个位置驱动的。< / p>

这些位置是分配导线的initial和always块。可以把它想象成使用离散门进行设计;在这种情况下，如果多次驱动相同的电线，也会导致问题。

所以你需要修改设计，所以每个wire / reg只能由一个always块或连续赋值驱动，其中initial块可能被转换为某个异步或同步复位，或初始值，如reg [5:0] countS := 0;。

在详细阐述设计愿景时出错

1 个答案: