Question

我刚开始使用Xilinx（ISE 14.7）在VHDL中编程。我已经可以编写一些项目了，但是我很难做到这一点。我的研究老师要求使用固定点的PWM。我设法单独使用它们，但我有一些错误，现在我无法知道导致实际问题的原因。错误是：

HDLCompiler：579 - ＆＃34; C：\ Users \ student \ Desktop \ Guilherme Moitas \ Projects \ pwm_fp \ pwm_fp.vhd＆＃34;第48行：条件信号分配中分配的元素数量不匹配错误：HDLCompiler：410 - ＆＃34; C：\ Users \ student \ Desktop \ Guilherme Moitas \ Projects \ pwm_fp \ pwm_fp.vhd＆＃34;第48行：表达式有18个元素;预期17

这就是我制作的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity pwm_fp is
Port (      clk      : in  STD_LOGIC;
         reset    : in  STD_LOGIC; 
         button_l : in  STD_LOGIC;  
         button_r : in  STD_LOGIC; 
         pwm      : out  STD_LOGIC);
 end pwm_fp;

 architecture Behavioral of pwm_fp is
  signal period:ufixed (12 downto -4);
  signal dcycle_max: ufixed (9 downto -4);
  signal dcycle_min: ufixed (8 downto -4);
  signal duty_in: ufixed (4 downto -4);
  signal pwm_reg,pwm_next:std_logic;
  signal duty_cycle,duty_cycle_next: ufixed (9 downto -4);
  signal counter,counter_next:ufixed (12 downto -4);
  signal tick:std_logic;
    --signal x: ufixed (12 downto -4);
 begin
 --register
     process(clk,reset)
          begin
               if reset = '1' then 
                    pwm_reg<='0';
                    counter<="00000000000000000";
                    duty_cycle<="00000000000000";
               elsif clk='1' and clk'event then
                     pwm_reg<=pwm_next;
                     counter<=counter_next;
                     duty_cycle<=duty_cycle_next;
               end if;
         end process;
                period <= to_ufixed (1001110001000.0000, period);
                dcycle_max <= to_ufixed (1000.00, dcycle_max);
                dcycle_min <= to_ufixed (500.00, dcycle_min);
                duty_in <= to_ufixed (20.00, duty_in);
                duty_cycle <= to_ufixed (0, duty_cycle);
                duty_cycle_next <= to_ufixed (0, duty_cycle_next);
                counter <= to_ufixed (000000000000.0000, counter);
                counter_next <= to_ufixed (0000000000000.0000,counter_next);
                --x <= to_ufixed (0000000000001.0000, x);

 counter_next <= "0" when counter = period else  -- this is line 48
                     counter + 1 ;
 tick<= '1' when counter= 0 else
         '0';

 --Changing Duty Cycle 
 process(button_l,button_r,tick,duty_cycle) 
    begin
         duty_cycle_next<=duty_cycle;
          if tick='1' then
               if button_l ='1' and (duty_cycle >dcycle_min) then
                      duty_cycle_next<= (duty_cycle-duty_in); 
               elsif button_r ='1' and (duty_cycle < dcycle_max) then
                      duty_cycle_next<= (duty_cycle+duty_in);
              end if;              
        end if;                            
 end process;
 --Buffer
 pwm<=pwm_reg;     
 pwm_next<= '1' when counter < duty_cycle else
                    '0';    
 end Behavioral;

我希望你能帮助我，对任何愚蠢的错误感到抱歉。从现在开始，谢谢！

使用固定点的PWM - Xilinx

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