非常感谢@KvanTTT @Ira Baxter。但我仍然感到不确定。我有两个步骤要做。首先，将AST更改或修改为另一个。其次，将修改后的AST合成或翻译成Verilog代码。第一步，我从YOSYS获得一个AST。给出一个如下例子：
1。 解析来自fulladder.v＆＃39;的Verilog输入。到AST表示。为module \ fulladder生成RTLIL表示＆＃39;。简化后转储Verilog AST：AST_MODULE [00bf5c30] str =＆＃39; \ fulladder＆＃39; AST_WIRE [00bf5d40] str =＆＃39; \ a＆＃39;输入端口= 1范围= [0：0] AST_WIRE [00bf5dc8] str =＆＃39; \ b＆＃39;输入端口= 2范围= [0：0] AST_WIRE [00bf5e50] str =＆＃39; \ cin＆＃39;输入端口= 3范围= [0：0] AST_WIRE [00bf5ed8] str =＆＃39; \ sum＆＃39;输出端口= 4范围= [0：0] AST_WIRE [00bf5f60] str =＆＃39; \ cout＆＃39;输出端口= 5范围= [0：0] AST_ASSIGN [00bf63a0] AST_CONCAT [00bf6070] AST_IDENTIFIER [00bf5fe8 - ＆gt; 00bf5ed8] str =＆＃39; \ sum＆＃39; AST_IDENTIFIER [00bf5cb8 - ＆gt; 00bf5f60] str =＆＃39; \ cout＆＃39; AST_ADD [00bf6318] AST_ADD [00bf6208] AST_IDENTIFIER [00bf60f8] - ＆gt; 00bf5d40] str =＆＃39; \ a＆＃39; AST_IDENTIFIER [00bf6180 - ＆gt; 00bf5dc8] str =＆＃39; \ b＆＃39; AST_IDENTIFIER [00bf6290 - ＆gt; 00bf5e50] str =＆＃39; \ cin＆＃39; ---结束AST DUMP ---成功完成了Verilog前端。
然后我需要做一些更改或修改到AST以获得另一个AST，我想要的是如下：
从fulladder_t.v解析Verilog输入＆＃39;到AST表示。为module \ fulladder_t生成RTLIL表示＆＃39;。简化后转储Verilog AST：AST_MODULE [00bf5c30] str =＆＃39; \ fulladder_t＆＃39; AST_WIRE [00bf6318] str =＆＃39; \ a＆＃39;输入端口= 1范围= [0：0] AST_WIRE [00bf6290] str =＆＃39; \ a_t＆＃39;输入端口= 2范围= [0：0] AST_WIRE [00bf6208] str =＆＃39; \ b＆＃39;输入端口= 3范围= [0：0] AST_WIRE [00bf6180] str =＆＃39; \ b_t＆＃39;输入端口= 4范围= [0：0] AST_WIRE [00bf60f8] str =＆＃39; \ cin＆＃39;输入端口= 5范围= [0：0] AST_WIRE [00bf6070] str =＆＃39; \ cin_t＆＃39;输入端口= 6范围= [0：0] AST_WIRE [00bf5cb8] str =＆＃39; \ sum＆＃39;输出端口= 7范围= [0：0] AST_WIRE [00bf5fe8] str =＆＃39; \ sum_t＆＃39;输出端口= 8范围= [0：0] AST_WIRE [00bf5f60] str =＆＃39; \ cout＆＃39;输出端口= 9范围= [0：0] AST_WIRE [00bf5ed8] str =＆＃39; \ cout_t＆＃39;输出端口= 10范围= [0：0] AST_ASSIGN [00bf7390] AST_CONCAT [00bf5dc8] AST_IDENTIFIER [00bf5e50 - ＆gt; 00bf5cb8] str =＆＃39; \ sum＆＃39; AST_IDENTIFIER [00bf63a0 - ＆gt; 00bf5f60] str =＆＃39; \ cout＆＃39; AST_ADD [00bf7308] AST_ADD [00bf71f8] AST_IDENTIFIER [00bf5d40 - ＆gt; 00bf6318] str =＆＃39; \ a＆＃39; AST_IDENTIFIER [00bf7170 - ＆gt; 00bf6208] str =＆＃39; \ b＆＃39; AST_IDENTIFIER [00bf7280 - ＆gt; 00bf60f8] str =＆＃39; \ cin＆＃39; AST_ASSIGN [00bf7748] AST_IDENTIFIER [00bf7418 - ＆gt; 00bf5fe8] str =＆＃39; \ sum_t＆＃39; AST_BIT_OR [00bf76c0] AST_BIT_OR [00bf75b0] AST_IDENTIFIER [00bf74a0 - ＆gt; 00bf6290] str =＆＃39; \ a_t＆＃39; AST_IDENTIFIER [00bf7528 - ＆gt; 00bf6180] str =＆＃39; \ b_t＆＃39; AST_IDENTIFIER [00bf7638 - ＆gt; 00bf6070] str =＆＃39; \ cin_t＆＃39; AST_ASSIGN [00c10b30] AST_IDENTIFIER [00bf77d0 - ＆gt; 00bf5ed8] str =＆＃39; \ cout_t＆＃39; AST_BIT_OR [00c10a] AST_BIT_OR [00c106f0] AST_BIT_OR [00c10338] AST_BIT_OR [00c0ff80] AST_BIT_OR [00c0fbc8] AST_BIT_OR [00c0f810] AST_BIT_OR [00c0f458] AST_BIT_OR [00c0f238] AST_BIT_AND [00bf7968] AST_IDENTIFIER [00bf7858]＆gt; 00bf6290] str =＆＃39; \ a_t＆＃39; AST_IDENTIFIER [00bf78e0 - ＆gt; 00bf6180] str =＆＃39; \ b_t＆＃39; AST_BIT_AND [00bf7b00] AST_IDENTIFIER [00bf79f0 - ＆gt; 00bf6180] str =＆＃39; \ b_t＆＃39; AST_IDENTIFIER [00bf7a78 - ＆gt; 00bf6070] str =＆＃39; \ cin_t＆＃39; AST_BIT_AND [00c0f3d0] AST_IDENTIFIER [00c0f2c0 - ＆gt; 00bf6290] str =＆＃39; \ a_t＆＃39; AST_IDENTIFIER [00c0f348 - ＆gt; 00bf6070] str =＆＃39; \ cin_t＆＃39; AST_BIT_AND [00c0f788] AST_BIT_AND [00c0f678] AST_IDENTIFIER [00c0f4e0 - ＆gt; 00bf6318] str =＆＃39; \ a＆＃39; AST_BIT_NOT [00c0f5f0] AST_IDENTIFIER [00c0f568 - ＆gt; 00bf60f8] str =＆＃39; \ cin＆＃39; AST_IDENTIFIER [00c0f700 - ＆gt; 00bf6180] str =＆＃39; \ b_t＆＃39; AST_BIT_AND [00c0fb40] AST_BIT_AND [00c0fa30] AST_BIT_NOT [00c0f920] AST_IDENTIFIER [00c0f898 - ＆gt; 00bf6318] str =＆＃39; \ a＆＃39; AST_IDENTIFIER [00c0f9a8 - ＆gt; 00bf60f8] str =＆＃39; \ cin＆＃39; AST_IDENTIFIER [00c0fab8 - ＆gt; 00bf6180] str =＆＃39; \ b_t＆＃39; AST_BIT_AND [00c0fef8] AST_BIT_AND [00c0fde8] AST_IDENTIFIER [00c0fc50 - ＆gt; 00bf6318] str =＆＃39; \ a＆＃39; AST_BIT_NOT [00c0fd60] AST_IDENTIFIER [00c0fcd8 - ＆gt; 00bf6208] str =＆＃39; \ b＆＃39; AST_IDENTIFIER [00c0fe70 - ＆gt; 00bf6070] str =＆＃39; \ cin_t＆＃39; AST_BIT_AND [00c102b0] AST_BIT_AND [00c101a0] AST_BIT_NOT [00c10090] AST_IDENTIFIER [00c10008 - ＆gt; 00bf6318] str =＆＃39; \ a＆＃39; AST_IDENTIFIER [00c10118 - ＆gt; 00bf6208] str =＆＃39; \ b＆＃39; AST_IDENTIFIER [00c10228 - ＆gt; 00bf6070] str =＆＃39; \ cin_t＆＃39; AST_BIT_AND [00c10668] AST_BIT_AND [00c10558] AST_IDENTIFIER [00c103c0 - ＆gt; 00bf6208] str =＆＃39; \ b＆＃39; AST_BIT_NOT [00c104d0] AST_IDENTIFIER [00c10448 - ＆gt; 00bf60f8] str =＆＃39; \ cin＆＃39; AST_IDENTIFIER [00c105e0 - ＆gt; 00bf6290] str =＆＃39; \ a_t＆＃39; AST_BIT_AND [00c10a20] AST_BIT_AND [00c109] AST_BIT_NOT [00c10800] AST_IDENTIFIER [00c10778] - ＆gt; 00bf6208] str =＆＃39; \ b＆＃39; AST_IDENTIFIER [00c10888 - ＆gt; 00bf60f8] str =＆＃39; \ cin＆＃39; AST_IDENTIFIER [00c10998 - ＆gt; 00bf6290] str =＆＃39; \ a_t＆＃39; ---结束AST DUMP ---成功完成了Verilog前端。
我该怎么办？ ANTLR或DMS可以完成这项任务吗？
第二步，我需要合成修改后的AST来生成Verilog代码，我该怎么办？