我实现了MIPS架构的流水线操作，并且我在Execute和Memory模块之间的锁存器中有过度使用。
这是我现在的代码：
module ex_mem(
input wire [1:0] ctlwb_out,
input wire [2:0] ctlm_out,
input wire [31:0] adder_out,
input wire aluzero,
input wire [31:0] aluout, readdat2,
input wire [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg branch, memread, memwrite,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result, rdata2out,
output reg [4:0] five_bit_muxout
);
initial begin
wb_ctlout <= 0;
branch <= 0;
memread <= 0;
memwrite <= 0;
add_result <= 0;
zero <= 0;
alu_result <= 0;
rdata2out <= 0;
five_bit_muxout <= 0;
end
always @ * begin
#1 //delay
wb_ctlout <= ctlwb_out;
branch <= ctlm_out[2]; //unsure ]
memread <= ctlm_out[1]; //unsure ] -- of correct order
memwrite <= ctlm_out[0]; //unsure ]
add_result <= adder_out;
zero <= aluzero;
alu_result <= aluout;
rdata2out <= readdat2;
five_bit_muxout <= muxout;
end
endmodule
我得到的错误是：
[放置30-58] IO放置是不可行的。未放置的终端（107）的数量>大于可用站点的数量（100）。 以下I / O端子组的容量不足： IO组：0：SioStd：LVCMOS18 VCCO = 1.8终止：0 TermDir：Out RangeId：1 Drv：12在设备上只有100个站点可用，但需要107个站点。 术语：add_result [0] 术语：add_result [1] 术语：add_result [2] 术语：add_result [3] 术语：add_result [4] 术语：add_result [5] 术语：add_result [6] 术语：add_result [7] 术语：add_result [8] 术语：add_result [9] 术语：add_result [10] 术语：add_result [11] 术语：add_result [12] 术语：add_result [13] 术语：add_result [14] 术语：add_result [15] 术语：add_result [16] 术语：add_result [17] 术语：add_result [18] 术语：add_result [19] 术语：add_result [20] 术语：add_result [21] 术语：add_result [22] 术语：add_result [23] 术语：add_result [24] 术语：add_result [25] 术语：add_result [26] 术语：add_result [27] 术语：add_result [28] 术语：add_result [29] 术语：add_result [30] 术语：add_result [31] 术语：alu_result [0] 术语：alu_result [1] 术语：alu_result [2] 术语：alu_result [3] 术语：alu_result [4] 术语：alu_result [5] 期限：alu_result [6] 期限：alu_result [7] 术语：alu_result [8] 术语：alu_result [9] 术语：alu_result [10] 期限：alu_result [11] 期限：alu_result [12] 期限：alu_result [13] 期限：alu_result [14] 期限：alu_result [15] 期限：alu_result [16] 期限：alu_result [17] 期限：alu_result [18] 术语：alu_result [19] 期限：alu_result [20] 术语：alu_result [21] 术语：alu_result [22] 期限：alu_result [23] 期限：alu_result [24] 期限：alu_result [25] 期限：alu_result [26] 期限：alu_result [27] 期限：alu_result [28] 期限：alu_result [29] 期限：alu_result [30] 期限：alu_result [31] 术语：rdata2out [0] 术语：rdata2out [1] 术语：rdata2out [2] 术语：rdata2out [3] 术语：rdata2out [4] 术语：rdata2out [5] 术语：rdata2out [6] 术语：rdata2out [7] 术语：rdata2out [8] 术语：rdata2out [9] 术语：rdata2out [10] 术语：rdata2out [11] 术语：rdata2out [12] 术语：rdata2out [13] 期限：rdata2out [14] 术语：rdata2out [15] 术语：rdata2out [16] 术语：rdata2out [17] 期限：rdata2out [18] 术语：rdata2out [19] 术语：rdata2out [20] 术语：rdata2out [21] 术语：rdata2out [22] 期限：rdata2out [23] 术语：rdata2out [24] 术语：rdata2out [25] 术语：rdata2out [26] 术语：rdata2out [27] 期限：rdata2out [28] 术语：rdata2out [29] 术语：rdata2out [30] 术语：rdata2out [31] 术语：five_bit_muxout [0] 术语：five_bit_muxout [1] 术语：five_bit_muxout [2] 术语：five_bit_muxout [3] 术语：five_bit_muxout [4] 术语：wb_ctlout [0] 术语：wb_ctlout [1] 术语：分支 术语：记忆 术语：memwrite 期限：和零
有人可以帮忙吗？感谢。
答案 0 :(得分：1)
module ex_mem(
input wire [1:0] ctlwb_out,
input wire [2:0] ctlm_out,
input wire [31:0] adder_out,
input wire aluzero,
input wire [31:0] aluout, readdat2,
input wire [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg branch, memread, memwrite,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result, rdata2out,
output reg [4:0] five_bit_muxout
);
always @ * begin
// #1 //delay
wb_ctlout = 0;
branch = 0;
memread = 0;
memwrite = 0;
add_result = 0;
zero = 0;
alu_result = 0;
rdata2out = 0;
five_bit_muxout = 0;
wb_ctlout = ctlwb_out;
branch = ctlm_out[2]; //unsure ]
memread = ctlm_out[1]; //unsure ] -- of correct order
memwrite = ctlm_out[0]; //unsure ]
add_result = adder_out;
zero = aluzero;
alu_result = aluout;
rdata2out = readdat2;
five_bit_muxout = muxout;
end
endmodule
对组合逻辑使用阻塞分配。
不要使用initial作为默认值，而是使用reset或代码中所示。