Question

因此，我正在处理一个采用同步输入的简单寄存器，并且一旦输入被置位，就会保持该状态，直到启用复位。

我的代码应该是非常自我解释的。这种产品检验会导致任何问题吗？

    module walk_reg(
        input Walk_Sync,    //pedestrian set walk-request
        input WR_Reset,     //FSM reset, for during the walk service
        input clk,      //clock
        output reg WR   //output
        );


    always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

    endmodule // walk_reg

编辑更改了变量名称，忘记在代码中更改

Answer 1

没有回答，但评论过多。

always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

与：

相同

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (!WR)    
    WR <= Walk_Sync;
end

如果没有条件，人字拖将保留其值。

来自duskwuff的更好的建议：

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (Walk_Sync)    
    WR <= 1'b1;
end

Answer 2

在旁注中，WR_Reset仅在时钟工作时才重置触发器。在大多数Flop设计中，我们使用ASYNC复位边沿检测，然后使用基于时钟的复位检测。

always @(posedge (clk)) vs always @(posedge (clk) or posedge(WR_Reset))

否则，使用WR进行条件赋值没问题。

使用reg输出作为输入Verilog

2 个答案: