Question

我正在尝试使用process语句在vhdl中编程。以下是我的vhdl代码

begin

dcm_clk PORT MAP(
    CLKIN1_IN => clk,
    RST_IN => reset,
    CLKOUT0_OUT => clk0_fast,
    CLKOUT1_OUT => clk0_dac,
    CLKOUT2_OUT => clk90_fast, --13.33MHz ; div =60
    CLKOUT3_OUT => clk_mux      --26.67MHz ; div =30 
);


process(clk_mux, reset)
begin
if (reset = '0') then
    if rising_edge(clk_mux) then
        if count_m = 0 then -- 0
            MUX_0 <= '1';
            count_m <= count_m + 1;
        elsif count_m = 29 then
            MUX_0 <= '0';
            count_m <= count_m + 1;
        elsif count_m = 57 then
            MUX_0 <= '1';
            count_m <= count_m + 1;
        elsif count_m = 86 then
            MUX_0 <= '0';
            count_m <= count_m + 1;
        elsif count_m = 115 then
            count_m <= (others => '0');         
    end if; -- end count_m
  end if; -- end clock

end if; -- end reset

count_m的值似乎停留在值＆＃39; 1＆＃39;。我不明白为什么计数器没有增量。任何帮助深表感谢。测试平台的输出如下所示

Answer 1

您的未标记流程仅为count_m的四个特定值递增count_m，而count_m = 1不是其中之一。

尝试：

UNLABELLED_PROCESS:
    process (clk_mux, reset)
    begin
        if (reset = '0') then
            if rising_edge(clk_mux) then
                count_m <= count_m + 1;
                if count_m = 0 then -- 0
                    MUX_0 <= '1';
                   --  count_m <= count_m + 1;
                elsif count_m = 29 then
                    MUX_0 <= '0';
                    count_m <= count_m + 1;
                elsif count_m = 57 then
                    MUX_0 <= '1';
                    -- count_m <= count_m + 1;
                elsif count_m = 86 then
                    MUX_0 <= '0';
                    -- count_m <= count_m + 1;
                elsif count_m = 115 then
                    count_m <= (others => '0');         
            end if; -- end count_m
          end if; -- end clock

        end if; -- end reset
    end process;

这样做的每一个clk_mux都会递增count_m，当值为115时，它会将它分配给所有'0'。

这就是：

如果我的时钟周期算术正确的话。请注意，count_m + 1到count_m的赋值被count_m = 115的if语句覆盖。您还可以看到MUX_0是一个触发器，它的输出在下一个clk_mux上升沿之后发生变化，指定了一个指定更改的count_m值。 / p>

调试帮助应该为应答读者提供通过提供Minimal, Complete, and Verifiable example来重新创建特定错误的能力。

在这种情况下，clk_mux的第二个过程是问题，四个信号声明具有必要的初始值（缺少任何重置动作）所有在实体和体系结构对中：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity no_mcve is
end entity;

-- dcm_clk PORT MAP(
--     CLKIN1_IN => clk,
--     RST_IN => reset,
--     CLKOUT0_OUT => clk0_fast,
--     CLKOUT1_OUT => clk0_dac,
--     CLKOUT2_OUT => clk90_fast, --13.33MHz ; div =60
--     CLKOUT3_OUT => clk_mux      --26.67MHz ; div =30
-- );

architecture foo of no_mcve is
    signal count_m: unsigned (9 downto 0) := (others => '0');
    signal clk_mux: std_logic := '0'; -- clock
    signal mux_0:   std_logic := '0';
    signal reset:   std_logic := '0';
begin

UNLABELLED_PROCESS:
    process (clk_mux, reset)
    begin
        if (reset = '0') then
            if rising_edge(clk_mux) then
                count_m <= count_m + 1;
                if count_m = 0 then -- 0
                    MUX_0 <= '1';
                   --  count_m <= count_m + 1;
                elsif count_m = 29 then
                    MUX_0 <= '0';
                    count_m <= count_m + 1;
                elsif count_m = 57 then
                    MUX_0 <= '1';
                    -- count_m <= count_m + 1;
                elsif count_m = 86 then
                    MUX_0 <= '0';
                    -- count_m <= count_m + 1;
                elsif count_m = 115 then
                    count_m <= (others => '0');         
            end if; -- end count_m
          end if; -- end clock

        end if; -- end reset
    end process;
CLOCK:
    process
    begin
        wait for 19.25 ns;
        clk_mux <= not clk_mux;
        if now > 7.3 us then
            wait;
        end if;
    end process;
end architecture;

VHDL：进程和计数器不起作用

1 个答案: