Question

所以我正在构建一个将无符号8位数除以53的除法器。它显示商和余数作为输出。我使用一个if / else语句来完成此任务。我在每个if / elseif / else语句附近声明语法错误，我收到语法错误，我找不到错误，我的语法错误在哪里？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity divider is
    Port ( input : in STD_LOGIC_VECTOR (7 downto 0);
           output : out STD_LOGIC_VECTOR (7 downto 0);
           r : out STD_LOGIC_VECTOR ( 7 downto 0));
end divider;

architecture Behavioral of divider is

signal input : unsigned(7 downto 0);
signal n : unsigned(7 downto 0);
signal quotient : unsigned(7 downto 0);
signal remainder : unsigned(7 downto 0);
signal a : unsigned(7 downto 0);
signal b : unsigned(7 downto 0);
signal c : unsigned(7 downto 0);
signal d : unsigned(7 downto 0);
signal zero : unsigned(7 downto 0);
signal one : unsigned(7 downto 0);
signal two : unsigned(7 downto 0);
signal three : unsigned(7 downto 0);
signal four : unsigned(7 downto 0);
signal x : unsigned(7 downto 0);
signal y : unsigned(7 downto 0);
signal z : unsigned(7 downto 0);
signal t : unsigned(7 downto 0);


begin
a <= "11010100"; -- 212
b <= "110011111"; -- 159
c <= "01101010"; -- 106
d <= "00110101"; -- 53
zero <= "0000000"; -- 0
one <= "00000001"; -- 1
two <= "00000010"; -- 2
three <= "00000011"; -- 3
four <= "00000100"; -- 4
x <= n - a; -- input - 212
y <= n - b; -- input - 159
z <= n - c; -- input - 106
t <= n - d; -- input - 53



input <= n;

if (x > zero) then
    quotient <= four;
    remainder <= n - a;

elsif (y = zero) then
    quotient <= three;
    remainder <= n - b;

elsif (z > zero) then
    quotient <= two;
    remainder <= n - c;

elsif (t > zero) then
    quotient <= one;
    remainder <= n - d;

else
    quotient <= zero;
    remainder <= n;
end if;

output <= quotient;
r <= remainder;

end behavioral;

Answer 1

分析：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity divider is
    port ( input:   in  std_logic_vector (7 downto 0);
           output:  out std_logic_vector (7 downto 0);
           r:       out std_logic_vector ( 7 downto 0)
    );
end divider;

architecture behavioral of divider is

--    signal input:  unsigned(7 downto 0);
    signal n:         unsigned(7 downto 0);
    signal quotient:  unsigned(7 downto 0);
    signal remainder: unsigned(7 downto 0);
    signal a:         unsigned(7 downto 0);
    signal b:         unsigned(7 downto 0);
    signal c:         unsigned(7 downto 0);
    signal d:         unsigned(7 downto 0);
    signal zero:      unsigned(7 downto 0);
    signal one:       unsigned(7 downto 0);
    signal two:       unsigned(7 downto 0);
    signal three:     unsigned(7 downto 0);
    signal four:      unsigned(7 downto 0);
    signal x:         unsigned(7 downto 0);
    signal y:         unsigned(7 downto 0);
    signal z:         unsigned(7 downto 0);
    signal t:         unsigned(7 downto 0);

begin

    a <=        "11010100"; -- 212  -- get the lengths right
    b <=        "10011111"; -- 159  -- should these be constants?
    c <=        "01101010"; -- 106
    d <=        "00110101"; -- 53
    zero <=     "00000000"; -- 0
    one <=      "00000001"; -- 1
    two <=      "00000010"; -- 2
    three <=    "00000011"; -- 3
    four <=     "00000100"; -- 4
    x <= n - a; -- input - 212
    y <= n - b; -- input - 159
    z <= n - c; -- input - 106
    t <= n - d; -- input - 53

    -- input <= n;  -- can't assign inputs

    process (x, zero, four, three, n, b, c, d)  -- need a process
    begin
        if x > zero then
            quotient <= four;
            remainder <= n - a;

        elsif y = zero then
            quotient <= three;
            remainder <= n - b;

        elsif z > zero then
            quotient <= two;
            remainder <= n - c;

        elsif t > zero then
            quotient <= one;
            remainder <= n - d;

        else
            quotient <= zero;
            remainder <= n;
        end if;
    end process;

    output <= std_logic_vector(quotient);      -- need type conversion
    r      <= std_logic_vector(remainder);     -- ditto

end architecture behavioral;

你有几个字符串文字的长度与他们的作业目标不匹配。

if语句需要处于一个过程中。

有一些丢失的类型转换。

其余的变化是风格和可读性。

Haven验证了它实现的算法。

VHDL if / else找不到语法错误

1 个答案: