Question

我有一个模块Decode和一个模块RegisterBank。解码将地址传递给寄存器，在寄存器中返回数据。我已尝试将这些模块互连，但我不知道此时我做错了什么。任何帮助将不胜感激！

我的解码模块：

module DecodeStage(  //Receives instruction and prepares the operands to be processed by ALU
input clk, 
//extract address, pass to register bank, receive back from register bank
input[31:0] InstrIn, //Extract operand register address from instruction 
output reg[3:0] address1_ds, //Pass to register bank
output reg[3:0] address2_ds, 
input[31:0] regval1_ds, //Receive values returned by the register bank
input[31:0] regval2_ds

);

wire [3:0] addr1; wire [3:0] addr2;
wire [31:0] outreg1;wire [31:0] outreg2;

//Connect Register Bank Module
RegisterBank register(
.rw_ds          (rw_ds),
.address1_ds    (addr1), //input[3:0]
.address2_ds    (addr2), //input[3:0]
.outval1_ds     (outreg1), //output reg[31:0]
.outval2_ds     (outreg2), //output reg[31:0]
);

//wire assigns
assign regval1_ds = outreg1;
assign regval2_ds = outreg2;
assign addr1 = address1_ds;
assign addr2 = address2_ds;


always @ (posedge clk)
begin   

    //Extract operand register address from instruction
    address1_ds = InstrIn[7:4];
    address2_ds = InstrIn[3:0];

end
endmodule

这是我的RegisterBank：

module RegisterBank(
input rw_ds, //boolean - 0 for read, 1 for write
input[3:0] address1_ds, //get address from decode
input[3:0] address2_ds, //get address from decode
output reg[31:0]outval1_ds, //output register data to decode
output reg[31:0]outval2_ds //output register data to decode
);

reg [31:0] register[0:15]; //array of sixteen 32 bit registers


always @ (posedge address1_ds, address2_ds, inval_ds, addr_wr_ds, inval_es, addr_wr_es) //WHAT SHOULD I MAKE THE ALWAYS TRIGGER ON
begin

    //declare what's in the registers
    register[0] = 0; register[1] = 1; register[2] = 2; register[3] = 3;
    register[4] = 4; register[5] = 5; register[6] = 6; register[7] = 7;
    register[8] = 8; register[9] = 9; register[10] = 10; register[11] = 11;
    register[12] = 12; register[13] = 13; register[14] = 14; register[15] = 15;

    //DECODE
    //If read, read values from registers
    if (rw_ds == 0)
    begin
        outval1_ds = register[address1_ds];
        outval2_ds = register[address2_ds];

    end

    //If write, write contents of address 1 to address 2
    if (rw_ds == 1)
    begin
        register[addr_wr_ds] = inval_ds;
    end


end

endmodule

基本上，address1_ds通过wire addr1发送到Register。寄存器发回outval1_ds，它是有线outreg1，输入到Decode为regval1。

Answer 1

RegisterBank register(
.rw_ds          (rw_ds),
.address1_ds    (addr1), //input[3:0]
.address2_ds    (addr2), //input[3:0]
.outval1_ds     (outreg1), //output reg[31:0]
.outval2_ds     (outreg2),//output reg[31:0]
);

1）从 RegisterBank 模块的实例化中删除 outreg2 信号后的额外逗号。

2）变量'addr_wr_es'，'inval_ds'，'addr_wr_ds'，' inval_es'尚未在 RegisterBank 模块中声明，但在灵敏度列表中使用。模块 DecodeStage 中的信号 rw_ds 尚未声明但已使用。 明确声明所有变量。

Verilog-2001添加了一个新的`default_nettype 选项，“ none 。”指定 none 选项告诉编译器所有变量必须显式声明，并且不推断默认类型。这主要是为了删除任何可能因拼写错误而产生的未声明变量。

修复这些将有助于编译和模拟代码。

Answer 2

删除这些额外的东西，连接它们就像分配

一样好

//wire assigns
assign regval1_ds = outreg1;
assign regval2_ds = outreg2;
assign addr1 = address1_ds;
assign addr2 = address2_ds;

互联模块连接

2 个答案: