Question

我编写了一个测试程序，在找到信号的上升沿时将引脚分配给1，在找到不同信号的下降沿时分配给0。

通过使用2个always语句，我得到了多个常量驱动程序错误。如何编辑我的代码，以便我只使用1个始终阻止而不会收到错误？

module clockedge(clock1, clock2, out);
input clock1;
input clock2;
output out;
reg out;

always@(posedge clock1) begin
    out=1;
end

always@(negedge clock2) begin
    out=0;
end

endmodule

我正在Quartus II中为Cyclone II编译。

我得到的错误：

错误（10028）：无法在clockedge.v（11）解析网络“out”的多个常量驱动程序
错误（10029）：clockedge.v（7）

Answer 1

您期待什么硬件？我想你可能会想出一些这样做的异步电路，但是它需要是异步的吗？这是一个可以满足您需求的同步电路：

module clockedge(clock, clock1, clock2, out);
  input clock;
  input clock1;
  input clock2;
  output out;

  reg out;
  reg clock1_d, clock1_dd, clock1_ddd;
  reg clock2_d, clock2_dd, clock2_ddd;
  wire up, dn;

  // I'd synchronise first...
  always@(posedge clock) begin
      clock1_d   <= clock1;
      clock1_dd  <= clock1_d;
      clock2_d   <= clock2;
      clock2_dd  <= clock2_d;
  end

  //...then we need synchronous edge detectors...
  always@(posedge clock) begin
      clock1_ddd <= clock1_dd;
      clock2_ddd <= clock2_dd;
  end
  assign up = ~clock1_ddd &  clock1_dd;
  assign dn =  clock2_ddd & ~clock2_dd;

  //..and here's an FSM that does the rest
  always@(posedge clock) begin
    if (up)
        out <= 1'b1;
      else
        if (dn)
          out <= 1'b0;
  end

endmodule

但你可能想要重置。

http://www.edaplayground.com/x/3GGS

Answer 2

也许你可以试试：

module clockedge(clock1, clock2, out);
input clock1;
input clock2;
output out;
reg out;

always@(posedge clock1 or negedge clock2) 
begin
if (clock1 == 1) out=1; // Means after a posedge, clock1 should be 1
if (clock2 == 0) out=0; // Means after a negedge, clock2 should be 0

end
endmodule

Verilog多个常数驱动程序

2 个答案: