Question

我试图用Verilog做一个简单的Master。现在，它应该只发送一个从地址。我的流程clock == 0似乎有问题。因为我收到以下错误消息： Error (10028): Can't resolve multiple constant drivers for net "sda_reg" at Master.v(33) 我已经读到，同时更改一个值（在这种情况下为sda_reg）时存在问题，但是由于sda_reg处于不同状态而被修改的事实，所以我没有提出问题：

代码：

module Master
(button,clk,scl,sda);


    inout scl;
    inout sda;
    input clk;
    input button;



    reg ack_reg;
    reg[2:0] ack_counter;
    reg sda_reg;
    reg scl_reg;

    reg[7:0] i2c_adress;
    reg read_write;


    //states
    reg[1:0] state;
    parameter idle=0, start=1, send=2;

    initial begin
            ack_reg = 1'b0;
            ack_counter = 3'b0;
            sda_reg = 1'b0;
            i2c_adress = 8'b11011101;
    end


    always@(posedge clk) begin
            case(state)
                idle: begin
                    if(button) begin
                            state <= start;
                        end
                end
                start: begin
                    sda_reg <= 1'b0;
                    state <= send;
                end /*
                send: begin
                    if(ack_counter == 8 && sda) begin
                            state <= idle;
                        end
                end */

            endcase
        end

    always@(clk == 0) begin
            case(state)
                send: begin
                    //Counter for 8 bits
                    ack_counter <= ack_counter +1;
                    //Getting the Most Important bit
                    sda_reg <= i2c_adress[7];
                    //Shifting Adress for one bit 
                    i2c_adress <= i2c_adress << 1;
                end
            endcase
        end

    //Wire data to output       
    assign sda = sda_reg;
    assign scl = clk;



endmodule

Answer 1

inout scl; // Why this bidirectional?
inout sda;

always@(clk == 0) // What does it mean?

由于sda是inout，因此必须使用输出三态缓冲区。从sda读取数据时，三态缓冲器输出设置为高Z（方向== 0）示例：

assign sda = (direction) ? sda_reg : 1'bZ;

在重新设计此代码之前，请阅读有关双向信号的信息。

无法解析网络“ sda_reg”的多个常量驱动程序

1 个答案: