Question

我有以下代码：

module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4);
// parameters
input clock, direction, readWrite;      
inout reg [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4;
inout reg [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4;

// code
always @(posedge clock) begin
    if(direction==1) begin          // left to right
        assign RA1 = LA1 | LA2 | LA3 | LA4;
        assign RD1 = LD1 | LD2 | LD3 | LD4;     
        assign { RA2, RA3, RA4 } = RA1;
        assign { RD2, RD3, RD4 } = RD1;     
    end else begin
        if(direction==1) begin      // right to left
            assign LA1 = RA1 | RA2 | RA3 | RA4;
            assign LD1 = RD1 | RD2 | RD3 | RD4;     
            assign { LA2, LA3, LA4 } = LA1;
            assign { LD2, LD3, LD4 } = LD1; 
        end
    end
end
endmodule

但是，在第二行，＆＃34; inout reg [7：0] LD1，......＆＃34;声明在VeritakWin 3.84F中抛出语法错误。（Veritak允许＆＃34;输出reg＆＃34;因为我在程序中的给定代码之后有类似的代码）。如果我删除＆＃34; reg＆＃34;，我会在分配行中收到错误。如果我删除＆＃34; inout＆＃34;，我显然会收到错误。我甚至尝试删除＆＃34;分配＆＃34;关键字，也可以替换＆＃34; =＆＃34;用＆＃34;＆lt; =＆＃34; ，但仍然存在错误。我究竟做错了什么？（我是Verilog的新手）

Answer 1

<!DOCTYPE html> <html> <head> <meta charset="utf-8"> <meta name="viewport" content="width=device-width"> <title>JS Bin</title> </head> <body> <div class="row"> <div class="col-1"> As a side note: for those using npm and looking for a quick, reliable and ready-made solution there's lodash.random that can be easily required with a super small footprint (it will import just the method itself and not the whole lodash). </div> <div class="col-2"> <img src="https://placeholdit.imgix.net/~text?txtsize=33&txt=150%C3%97150&w=150&h=150"> </div> <div class="col-3"> As a side note: for those using npm and looking for a quick, reliable and ready-made solution there's lodash.random that can be easily required with a super small footprint (it will import just the method itself and not the whole lodash). </div> </div> </body> </html>个端口不能是inout类型。您用于为reg端口分配值的assign类型称为程序连续分配，但这种端口不允许这样做。您必须使用连续分配。在您的代码中：

inout

请注意，您无法同时读取和写入module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4); // parameters input clock, direction, readWrite; inout [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4; inout [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4; // left to right assign RA1 = (direction) ? (LA1 | LA2 | LA3 | LA4) : 'bz; assign RD1 = (direction) ? (LD1 | LD2 | LD3 | LD4) : 'bz; assign { RA2, RA3, RA4 } = (direction) ? RA1 : 'bz; assign { RD2, RD3, RD4 } = (direction) ? RD1 : 'bz; // right to left assign LA1 = (!direction) ? (RA1 | RA2 | RA3 | RA4) : 'bz; assign LD1 = (!direction) ? (RD1 | RD2 | RD3 | RD4) : 'bz; assign { LA2, LA3, LA4 } = (!direction) ? LA1 : 'bz; assign { LD2, LD3, LD4 } = (!direction) ? LD1 : 'bz; endmodule端口，因此在读取时会设置高阻抗值。

如何在Verilog中使用inout和reg

1 个答案: