Question

我有一个带有层次结构的节奏示意图。我能够在命令行以批处理模式运行si netlister，以生成分层verilog网表。我想知道是否有人知道是否有可能生产一个扁平的verilog网表。我尝试过各种各样的选择，但似乎无法让它发挥作用。谷歌搜索似乎对这是否可能提出了不同的看法。

我的用于分层运行的si.env文件如下：

simLibName = "myLib"
simCellName = "myCell"
simViewName = "schematic"
simSimulator = "verilog"
simNotIncremental = 't
simReNetlistAll = 't
simViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simStopList = '("functional" "verilog" "symbol")
simNetlistHier = t
simVerilogLaiLmsiNetlisting = 'nil
verilogSimViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simVerilogAutoNetlisting = 't
simVerilogTestFixtureFlag = 'nil
simVerilogTestFixtureTemplate = "All"
simVerilogNetlistExplicit = 't
hnlVerilogTermSyncUp = 'nil
simVerilogFlattenBuses = 'nil
vtoolsUseUpperCaseFlag = 'nil
hnlVerilogCreatePM = 'nil
simVerilogTopLevelModuleName = ""
simHierarchyPrefix = ""
simNCVerilogHierPrefix = ""
verilogSimStopList = '("functional" "verilog" "symbol")
simVerilogPwrNetList = '("vddin_sub!" "vddout_sub!" "vddin!" "vddout!" "vddin_sub" "vddout_sub" "vddin" "vddout" "vddfx")
simVerilogGndNetList = '("vssfx!" "vss_sub!" "vssfx" "vss_sub")
vtoolsifForceReNetlisting = 'nil
simVerilogLibNames = '("stdcell_lib")
vlogifInternalTestFixtureFlag = 'nil
simVerilogBusJustificationStr = "U"
simVerilogTestFixtureTemplate = "All"
simVerilogDropPortRange = 't
simVerilogHandleUseLib = 'nil
simVerilogHandleAliasPort = 't
simVerilogPrintStimulusNameMappingTable = 'nil
simVerilogProcessNullPorts = 'nil
simVerilogIncrementalNetlistConfigList = 'nil
hnlVerilogNetlistStopCellImplicit = 'nil
simVerilogOverWriteSchTimeScale = 'nil
vlogifCompatibilityMode = "4.0"
simVerilogHandleSwitchRCData = 'nil
vlogifUseAssignsForAlias = 'nil
vlogifDeclareGlobalNetLocal = 'nil
vlogifSkipTimingInfo = 'nil
simVerilogEnableEscapeNameMapping = 't
simVerilogStopAfterCompilation = 't
simVerilogVhdlImport = 'nil
simVerilogTopCellCounter = 0
hnlSupportIterInst = 'nil

说实话，我不知道这些选项有多少。我可能已经定义了我不需要的东西。我真的只想把它放到网表上......不需要任何设置来进行模拟。

谷歌搜索显示我需要在某些地方设置fnl *而不是hnl *，但没有什么特别关于使这个扁平网表正常工作的配方。

想知道是否有人有这方面的经验，并能够使扁平的verilog网络列表正常工作。

谢谢！

Answer 1

终于能够从节奏中得到一个直接的答案。不幸的是，si网表不能创建一个扁平的verilog网表。许多人已经要求添加此功能，但它没有得到积极处理。

cadence netlister si能产生扁平的verilog网表吗？

1 个答案: