Question

我在VHDL中有一段代码：

我想交换signalIn(0)和signalIn(1)值。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SwapFP is
port(clockIn:in std_logic);
end SwapFP;

architecture Behavioral of SwapFP is    

signal tempOne,tempTwo,a1,a2 : STD_LOGIC_VECTOR(31 DOWNTO 0);  

signal state : integer range 0 to 7 := 0;

begin 

  process(clockIn) is
  type floatingPointArray is array(1 downto 0) of std_logic_vector(31 downto 0);
  variable signalIn : floatingPointArray;

  begin

  signalIn(0) := X"3D52CEF8";
  signalIn(1) := X"3FBC9F1A";

  if rising_edge(clockIn) then

    case state is

    when 0 =>
        tempOne <= signalIn(0);
        tempTwo <= signalIn(1);
        state <= 1;
    when 1 =>
        signalIn(1) := tempOne;
        signalIn(0) := tempTwo;
        state <= 2;

    when 2 =>
        a1 <= signalIn(0);
        a2 <= signalIn(1);
        state <= 3;
    when others =>

    end case;

  end if;  

  end process;

end Behavioral;

在a1和a2信号中，我得到原始值X＆＃34; 3D52CEF8＆＃34;和X＆＃34; 3FBC9F1A＆＃34;分别。意味着不会发生交换。为什么会这样？

Answer 1

每次进程运行时，都会在进程顶部对signalIn进行变量赋值。如果state为2，则signalIn等于state时分配给1的值会被此初始分配覆盖。

您可以更轻松地交换两个项目：

process (clk)
begin
  if (rising_edge(clk)) then
    signalIn(0) <= signalIn(1);
    signalIn(1) <= signalIn(0);
  end if;
end process;

这是有效的，因为使用<=的信号分配不会立即发生，而是计划在进程运行后进行。

交换数组中的元素 - VHDL

1 个答案: