Question

这里有完整的错误：错误：HDLParsers：808 - ＆＃34; C：/ Users / vROG / Desktop /.../ CacheController.vhd＆＃34;第72行=在这种情况下不能有这样的操作数。

如果我被使用了，我会理解如何解决这个问题＆＃39; +＆＃39;或＆＃39; *＆＃39;，但等号？

正如您所知，代码几乎没有接近完全，但我无法理解为什么我的第二个嵌套如果不能正常工作。我已经尝试将dirtyBIT转换为int类型，但它仍然给我同样的错误，这让我相信我在某处犯了一个小错误。

已修复（使用user1155120＆＃39;建议）但是如何解决偏移和标记问题？

architecture Behavioral of CacheController is

signal tagFROMCPU :  STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);

TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state    : STATETYPE;

--Variables
signal dirtyBIT: std_logic_vector (7 downto 0);
signal validBIT: std_logic_vector (7 downto 0);

TYPE tag is array (7 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
TYPE offset is array (7 downto 0) of STD_LOGIC_VECTOR(4 downto 0);

signal myTag: tag;
signal myOFFSET : offset;
    begin

--STATE MACHINE
process(clk)    
begin
    if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1
        if ((myTag(to_integer(unsigned(indexFROMCPU)) = tagFROMCPU)) then
        --HIT
        else
            present_state <= state_1;
        end if;
    elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2

        if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
            present_state <= state_0;
        else
            present_state <= state_2;
        end if;

    elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
            present_state <= state_1;
    end if;
end process;


end Behavioral;

旧代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity CacheController is
Port (
        clk         : in  STD_LOGIC;
        CPU_addr    : in  STD_LOGIC_VECTOR (15 downto 0);
        CPU_WR_RD   : in  STD_LOGIC;
        CPU_CS      : in  STD_LOGIC;

        CPU_RDY     : out STD_LOGIC;

        SDRAM_Addr  : out  STD_LOGIC_VECTOR (15 downto 0);
        SDRAM_WR_RD : out  STD_LOGIC;
        SDRAM_MSTRB : out  STD_LOGIC;

        MUX1,MUX2   : out STD_LOGIC;

        SRAM_Addr   : out  STD_LOGIC_VECTOR (7 downto 0);
        SRAM_WEN    : out  STD_LOGIC

);

end CacheController;

architecture Behavioral of CacheController is

signal tagFROMCPU :  STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);

TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state    : STATETYPE;

--Variables to emulate SRAM
TYPE dirtyBIT is array (7 downto 0) of std_logic;
TYPE validBIT is array (7 downto 0) of std_logic;
TYPE tag is array (7 downto 0,7 downto 0) of std_logic;
TYPE offset is array (7 downto 0,4 downto 0) of std_logic;

begin

--STATE MACHINE
process(clk)    
begin
    if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1

    elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2

        if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
            present_state <= state_0;
        else
            present_state <= state_2;
        end if;

    elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
            present_state <= state_1;
    end if;
end process;


end Behavioral;

Answer 1

运算符重载决策（对于＆＃34; =＆＃34;运算符）要求使用匹配的签名声明函数（左右输入的类型和返回类型）。

        if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then

更改dirtyBit的声明：

--Variables to emulate SRAM
-- TYPE dirtyBIT is array (7 downto 0) of std_logic;
signal dirtyBIT: std_logic_vector (7 downto 0);

您的代码分析。我建议对其他类型声明（validBIT，tag和offset）进行类似处理。

看起来应该有一个使用offset的数组类型。可以更改类型名称以将offset保留为信号名称。

=在这种情况下不能有这样的操作数

1 个答案: