错误：*在此上下文中不能有这样的操作数

Question

我试图将std_logic_vector与negatif数字相乘：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul_main is
    Port ( a :in  STD_LOGIC_VECTOR( 0 to 7);
        clk: in  STD_LOGIC;
           c :out STD_LOGIC_VECTOR(0 to 15)
        );
end mul_main;

architecture Behavioral of mul_main is

begin
p: process(clk)
begin
if (clk' event and clk='1') then
c <= (-2)* a;
end if;
end process;

end Behavioral;

但是，我收到了这个错误： *不能有这样的操作数 上下文

实际上，我想将std_logic_vector与positif或 不幸的是，我没有得到同样的问题。 你能帮我吗？

提前致谢

Answer 1

没有使用universal_integer和std_logic_vector的操作数定义的乘法运算（“*”）。

std_logic_arith有

function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;

function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;

而std_logic_unsigned提供：

function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

将常量的参数更改为std_logic_vector：

c <= std_logic_vector(conv_unsigned(-2,a'LENGTH)) * a;

并模拟：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul_main is
    Port ( a :in  STD_LOGIC_VECTOR( 0 to 7);
        clk: in  STD_LOGIC;
           c :out STD_LOGIC_VECTOR(0 to 15)
        );
end mul_main;

architecture Behavioral of mul_main is

begin
p: process(clk)
begin
if (clk' event and clk='1') then
    c <= std_logic_vector(conv_unsigned(-2,a'LENGTH)) * a;
end if;
end process;

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity mul_tb is
end entity;

architecture foo of mul_tb is
    signal a:       std_logic_vector (0 to 7) := x"42";
    signal clk:     std_logic;
    signal c:       std_logic_vector (0 to 15);
begin
DUT:
    entity work.mul_main
        port map (
        a => a,
        clk => clk,
        c => c
        );

end architecture;

  

david_koontz @ Macbook：nvc -a mul_main.vhdl
  david_koontz @ Macbook：nvc -e mul_tb
  /Users/david_koontz/share/clang+llvm-3.3-x86_64-apple-darwin12/bin/opt -O2 -o /Users/david_koontz/Desktop/work/_WORK.MUL_TB.final.bc / Users / david_koontz / Desktop / work /_WORK.MUL_TB.elab.bc
  david_koontz @ Macbook：nvc -r mul_tb
  david_koontz @ Macbook：

成功。

你会注意到你的产品是无符号的，因为一切都是std_logic_vector而不是因为使用了conv_unsigned。要获得已签名的产品，您要使用签名值（并使用conv_signed）。

转换为使用已签名并获得签名扩展名：

生成两个补码输出为std_logic_vector

通过替换上下文子句中的use子句，将用于算术的包从存放在库ieee中的Synopsys包修改为实际的IEEE numeric_std包来生成此波形：

use IEEE.numeric_std.all;
-- use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_signed.all;

在mul_main中修改进程p：

p: 
    process(clk)
    begin
        if (clk' event and clk='1') then
            c <= std_logic_vector(
                to_signed(-2,a'LENGTH) * signed(a)
                ) ;
        end if;
    end process;

赋值给c的右侧表达式将常量-2转换为带符号的操作数，将std_logic_vector转换为带符号的操作数，将两个操作数相乘并将结果转换回std_logic_vector。一切皆有可能因为std_logic_vector和签名密切相关。