LLVM tablegen中InstrStage中的循环和NextCycles有什么区别？

Question

我正在尝试学习LLVM tablegen。现在我正试图了解如何定义指令阶段。我在llvm/include/llvm/Target/TargetItinerary.td中找到了以下评论：

// Instruction stage - These values represent a non-pipelined step in
// the execution of an instruction.  Cycles represents the number of
// discrete time slots needed to complete the stage.  Units represent
// the choice of functional units that can be used to complete the
// stage.  Eg. IntUnit1, IntUnit2. NextCycles indicates how many
// cycles should elapse from the start of this stage to the start of
// the next stage in the itinerary.  For example:
//
// A stage is specified in one of two ways:
//
//   InstrStage<1, [FU_x, FU_y]>     - TimeInc defaults to Cycles
//   InstrStage<1, [FU_x, FU_y], 0>  - TimeInc explicit
//

循环和NextCycle有什么区别？在我看来他们是一回事。我错过了什么？

感谢任何帮助。