在vhdl的行为中可以有多少个进程？

Question

我想减慢clk ...并接受输入

entity q1 is
    Port ( clk: in std_logic;
              a0,a1,a2,a3,a4,a5,a6,a7,a8,a9 : in  STD_LOGIC_VECTOR (3 downto 0);
           b0,b1,b2,b3,b4,b5,b6,b7,b8,b9 : in  STD_LOGIC_VECTOR (3 downto 0);
           y0,y1,y2,y3,y4,y5,y6,y7,y8,y9 : out  STD_LOGIC_VECTOR (6 downto 0));
end q1;

architecture Behavioral of q1 is
signal counter : std_logic_vector(9 downto 0)='0000000000';
signal clk_en: std_logic='0';
process(clk)
begin
     if (clk'event and clk='1') then
            counter <= counter +1;
            if (counter = 0) then
                clk_en <= '1';
            else clk_en='0' 
            end if ;
      end if;
end process;



end Behavioral;