Question

我正在编程VHDL，编译测试平台时遇到问题。收到以下错误：

错误（10327）：在comparador_12_tb.vhd（56）处出现VHDL错误：无法确定运营商的定义＆＃34;＆＃34;＆amp;＆＃34;＆＃34; - 找到0个可能的定义

代码

library ieee;
use ieee.std_logic_1164.all;

entity comparador_12 is
port( num1 : in std_logic_vector(3 downto 0);  
      num2 : in std_logic_vector(3 downto 0);
        clock : in std_logic;
      menor : out std_logic;   
      igual : out std_logic;   
      mayor : out std_logic
       );
end comparador_12;

architecture behavioral of comparador_12 is
begin
    process(num1,num2)
        begin    
            if (num1&num1&num1 > num2&num2&num2 ) then  
                menor <= '0';
                igual <= '0';
                mayor <= '1';
            elsif (num1&num1&num1 < num2&num2&num2) then    
                menor <= '1';
                igual <= '0';
                mayor <= '0';
            else    
                menor <= '0';
                igual <= '1';
                mayor <= '0';           
        end if;
    end process;   
end behavioral;

测试平台

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY comparador_12_tb IS
END comparador_12_tb;

ARCHITECTURE behavioral OF comparador_12_tb IS
-- constants                                                 
-- signals                                                   
SIGNAL igual : STD_LOGIC;
SIGNAL mayor : STD_LOGIC;
SIGNAL menor : STD_LOGIC;
SIGNAL num1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL num2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal clk : std_logic := '0';
constant clk_period : time := 20 ns;
signal x,y : std_logic;

COMPONENT comparador_12
    PORT (
    igual : BUFFER STD_LOGIC;
    mayor : BUFFER STD_LOGIC;
    menor : BUFFER STD_LOGIC;
    num1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    num2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    uut : comparador_12
    PORT MAP (
-- list connections between master ports and signals
    igual => igual,
    mayor => mayor,
    menor => menor,
    num1 => num1,
    num2 => num2
    );

clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  
        clk <= '1';
        wait for clk_period/2;  
end process;

tb : process
begin
        num1 <= "1001";
        num1 <= "1100";
        num1 <= "0100";
        num2 <= "1110";
        num2 <= "1101";
        num2 <= "1000";
        x <= num1&num1&num1;
        y <= num2&num2&num2;
    wait for 10 ns;
end process;            
END behavioral;

Answer 1

查看测试平台中的以下信号声明：

signal num1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal x,y : std_logic;

代码：

x <= num1&num1&num1;

&是连接运算符。在这种情况下，您将4位向量与自身连接起来，创建一个12位向量。然后，您将结果分配给一位std_logic信号。我不确定你会在这里发生什么，但这就是错误的原因。

与运营商＆＃34;＆＃34;＆amp;＆＃34;＆＃34;＆＃34;＆＃34;编译错误VHDL

1 个答案: