我试图用Altera的Quartus和Modelsim模拟RAM内存。问题在于，当我在测试台中为data_inout分配值并进行模拟时，波总是处于'U'状态。当我执行data_inout＆lt; =“0000000000001010”时，它不会取任何值;例如，如果我使用data_inout＆lt; = aux_data;我想要的只是测试它在数组上写一些值，然后阅读它们进行大学练习，没什么特别的。知道如何模拟吗？
感谢。
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_program is
port(
dir : in std_logic_vector (7 downto 0);
read_write,cs : in std_logic;
data_inout : inout std_logic_vector (15 downto 0)
);
end entity ram_program;
architecture code_ram_program of ram_program is
type tipo_ram is array (255 downto 0) of std_logic_vector (15 downto 0);
signal ram : tipo_ram;
begin
MEM_RAM: process (cs,read_write,datos_in_out,dir)
begin
if (cs = '1' and read_write = '1') then
ram(to_integer(unsigned(dir))) <= data_inout;
end if;
if (cs = '1' and read_write = '0') then
data_inout <= ram(to_integer(unsigned(dir)));
end if;
end process MEM_RAM;
end architecture code_ram_program;