Question

问题：在RTL代码中，如何确定将在其中生成的触发器数量合成

例如，在下面的代码中，如何在合成期间定义触发器的数量？

LIBRARY ieee;
USE ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
-- Entity for ALU component
-- Use this Entity for your C&A project


ENTITY ALU IS
  PORT(
    reset_n     : in std_logic;
    clk         : in std_logic;
    OperandA    : in std_logic_vector(3 downto 0);
    OperandB    : in std_logic_vector(3 downto 0);
    Operation   : in std_logic_vector(2 downto 0);
    Start       : in std_logic;
Result_Low        : out std_logic_vector(3 downto 0);
Result_High        : out std_logic_vector(3 downto 0);
Ready        : out std_logic;
Errorsig        : out std_Logic);
END ALU;
ARCHITECTURE behavioral OF ALU IS


 signal ready_stored :std_logic;
 signal t_Ready :std_logic;
 signal sum   : std_logic_vector(3 downto 0);
 signal carry : std_logic_vector(3 downto 0);
 signal sub   : std_logic_vector(3 downto 0):="0000";
 signal borrow: std_logic_vector(3 downto 0):="0000"; 

   component fulladder is 
    PORT(
    p: in std_logic; 
    a: IN std_logic;
    b: IN std_logic;
    cin : IN std_logic;
    c, s: OUT std_logic);
  END component;
   component halfadder is
   PORT(

  a: IN std_logic;
  b: IN std_logic;
  c, s: OUT std_logic);
  END component;
  component orgate is
  PORT(
   a: IN std_logic;
   b: IN std_logic;
   y: OUT std_logic);
   END component;
   component xorgate is 
      port(a : in std_logic;
           b : in std_logic;
           y : out std_logic
           );
       end component;

begin

-- port maps for full adder
 F1: fulladder 
port map ('0','0',OperandA(0),OperandB(0),carry(0),sum(0));

 F2: fulladder    
port map ('0',carry(0),OperandA(1),OperandB(1),carry(1),sum(1));

 F3: fulladder 
port map ('0',carry(1),OperandA(2),OperandB(2),carry(2),sum(2));

 F4: fulladder 
port map ('0',carry(2),OperandA(3),OperandB(3),carry(3),sum(3));

   -- port maps for division

  F5: fulladder
  port map ( '1','1',OperandB(0),OperandA(0),borrow(0),sub(0));

  F6: fulladder   
  port map ('1',borrow(0),OperandB(1),OperandA(1),borrow(1),sub(1));

  F7: fulladder
  port map ('1',borrow(1),OperandB(2),OperandA(2),borrow(2),sub(2));

  F8: fulladder 
  port map ('1',borrow(2),OperandB(3),OperandA(3),borrow(3),sub(3));

  Ready <= t_Ready ;

 process (OperandA,OperandB,reset_n,clk,operation,Start)
variable temp_Low: std_logic_vector(3 downto 0);
variable temp_High: std_logic_vector(3 downto 0);
variable loop_nr : integer range 0 to 15;
variable pv,bp   : std_logic_vector(7 downto 0);
variable f   : std_logic_vector(7 downto 0);
variable cout   : std_logic_vector(8 downto 0);
variable subtraction    : std_logic_vector(3 downto 0);
variable Quotient : std_logic_vector(3 downto 0) := "0000";
variable loop_m : integer range 0 to 15;

    begin
     if (reset_n = '0' ) then
        Result_Low <= "0000";
        Result_High <= "0000";
        Errorsig <= '0';
         t_Ready <= '0';
      elsif (clk'event and clk='1' ) then 
          if (start= '1') then  
                 case Operation is

         --Shift To Left

    when "001" => 
   loop_nr := to_integer(unsigned(OperandB));
for i in 0 to loop_nr loop 
if i = 0 then 
temp_Low := OperandA;
temp_High := "0000";
else  
temp_High := temp_High(2 downto 0)& temp_Low(3);
temp_Low := temp_Low(2 downto 0) &'0';

end if;
end loop;
Result_High <= temp_High;
Result_Low <= temp_Low;
t_Ready <= '1';
Errorsig <= '0';

     --Shift To Right 
   when "010" =>
 loop_nr := to_integer(unsigned(OperandB));
for i in 0 to loop_nr loop 
if i = 0 then 
 temp_Low := OperandA;
temp_High := "0000";
else  
temp_Low := '0' & temp_Low(3 downto 1) ;
temp_High := '0' & temp_High(3 downto 1);
end if;
end loop;
Result_High <= temp_High;
Result_Low <= temp_Low;
t_Ready <= '1';
Errorsig <= '0';

         -- XOR
when "011" => 
Result_Low <= ((not OperandA) and OperandB)or(OperandA and (not OperandB));
Result_High <= (others => '0');
t_Ready <= '1';
Errorsig <= '0';

                --Full Adder
when "100" => 
temp_High :="0000";
Result_Low <= sum(3 downto 0);
temp_High := temp_High(3 downto 1) & carry(3);
Result_High <= temp_High;
t_Ready <= '1';
Errorsig <= '0';



when others =>
Result_Low <= (others => '0');
t_Ready <= '0';
Errorsig <= '0';
 end case; 



  elsif ready_stored ='0' and t_Ready = '1' then
  t_Ready <= '1';
   else t_Ready <= '0';
    end if; 
    ready_stored <= t_Ready ;
    end if;
       end process; 
END behavioral;

Answer 1

以下是一般程序：

找到你的时钟流程;你只有一个（我认为你只询问过程，而不是加法器实例化）
展开循环（手动）。这很重要 - 第一次和最后一次迭代可能不同
如果你有一个在写入之前读取的信号或变量，那么这意味着从过程的先前“执行”开始记忆状态，合成器将为该信号或变量创建一个寄存器。

应该在所有情况下工作，但你的代码有点混乱，我没有详细阅读。 'mess'意味着合成器可能会混淆并做一些你不期望的事情。为什么敏感列表中有OperandA，OperandB，operation和Start？看起来你可以摆脱它们。您应该重新缩进代码以使其更具可读性。

vhdl中生成的触发器数量

1 个答案: