4位幅度比较器VHDL

时间:2015-06-27 19:45:51

标签: vhdl comparator magnitude

我必须在VHDL中制作一个4位大小的比较器,只有并发语句(如果/ else或if / when则没有。)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Exercise is
port (  A : in std_logic_vector (3 downto 0);
        B : in std_logic_vector (3 downto 0);
        Ag : out std_logic;
        Bg : out std_logic;
        AeqB: out std_logic
       );   
end Exercise;

architecture Comparator of Exercise is

begin
    Ag <= '1'when (A>B) else '0'; 
    Bg <= '1' when (B>A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B>A 
    AeqB<= '1' when (A=B) else '0'; 
end Comparator; 

问题是我需要计算std_logic(U,X,Z,W,L,H, - )的所有其他值,我知道有others但是无法弄明白如何使用with/select语句创建比较器。

由于

2 个答案:

答案 0 :(得分:0)

一般情况下,您可以“转换”&#39; std_logic可以使用0函数在1to_01中使用的各种值。我认为它在numeric_std包中。

答案 1 :(得分:0)

library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity comp_4 is
    port (  A:IN STD_LOGIC_VECTOR(0 to 3);
        B:IN STD_LOGIC_VECTOR(0 to 3);
        ET:OUT STD_LOGIC;
        GT:OUT STD_LOGIC;
        LT:OUT STD_LOGIC);

    end comp_4;

    architecture dataflow of comp_4 is

    begin
    with A-B(0 to 3) select

    ET <=   '1' when "0000",
        '0' when others;

    with A > B select

    GT <=   '1' when true,
        '0' when others;

    with A < B select

    LT <=   '1' when true,
        '0' when others;

    end dataflow;