一个3级比较器

时间:2016-02-09 01:18:06

标签: compare vhdl

我想制作一个具有一定容差的比较器。

我已经把这两个信号区别开了(希望如此) 现在我想比较一个数字(将在稍后决定)并分别转发相等的note和可接受的信号。

我已让评论部分帮助您了解我的方法。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity threelvlcomp is
    port ( 
        input1    : in  std_logic_vector(15 downto 0);
        input2    : in  std_logic_vector(15 downto 0);
        outputeq  : out std_logic;
        outputneq : out std_logic
    );
end threelvlcomp;

architecture Behavioral of threelvlcomp is

signal temp : std_logic_vector(15 downto 0);
signal dif  : std_logic_vector(15 downto 0);
--CONSTANT limit      : INTEGER := 1;

begin

  dif <= std_logic_vector(unsigned(input1)) + std_logic_vector(unsigned(not(input2) + 1));
  --dif <= input1 + not(input2)+ "1";
  --dif <= input1 + not(input2) + "1"; 

    outputeq <= '1' when dif < '1'  else
            '0';
        outputneq <= '1' when dif > '1' else
            '0';


-- IF dif = "0000" THEN
-- outputeq   <= '1';
-- outputneq  <= '0';
-- outputacc  <= '0';
--ELSE IF dif /= '0' THEN
-- outputeq   <= '0';
-- outputneq  <= '1';
--outputacc  <= '0';
--ELSE IF dif <= "0.5"; 
-- outputeq   <= '0';
-- outputneq  <= '0';
-- outputacc  <= '1';
--ELSE
-- outputeq   <= '1';
-- outputneq  <= '1';
-- outputacc  <= '1';
--END IF; 

--  If(dif = 0) then outputeq <='1'; else outputeq <= '0';end if;
--  If(dif >= -0.5 and dif <= 0.5) then outputacc <='1'; else outputacc <= '0';end if;
--  If(dif /= 0) then outputneq <='1' else outputneq <= '0';end if;

end Behavioral;

1 个答案:

答案 0 :(得分:0)

我还没有测试过这段代码。但对我来说,这似乎是你想要做的。它应该至少可以帮助您解决签名/未签名问题。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all; --do not use this it is confusing you

entity threelvlcomp is
    port ( 
        input1    : in  std_logic_vector(15 downto 0);
        input2    : in  std_logic_vector(15 downto 0);
        outputeq  : out std_logic;
        outputneq : out std_logic
    );
end threelvlcomp;

architecture Behavioral of threelvlcomp is

signal temp : unsigned(15 downto 0);
signal dif  : signed(16 downto 0);
--CONSTANT limit      : INTEGER := 1;

begin

-- you want a signed number here so we need to signed extend with a zero
  dif <= (signed('0'input1)) + (not signed('0'&input2)) + 1; 
  --dif <= input1 + not(input2)+ "1";
  --dif <= input1 + not(input2) + "1"; 

    outputeq <= '1' when dif < 1  else
            '0';
        outputneq <= '1' when dif > 1 else
            '0';
end Behavioral;