Question

我需要在文件中逐个从verilog模块中编写2个变量。变量在一个周期信号freq_rdy的上升沿更新。我正在使用以下代码。

integer write_file1;
integer freq_rdy_1,freq_rdy_2;

initial begin

write_file1 = $fopen("frequencies.txt","w");        
freq_rdy_1 = testbench.UUT.read_controller.freq_rdy;
freq_rdy_2 = testbench.UUT.read_controller_2.freq_rdy;

@(posedge freq_rdy_1)
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i); 

@(posedge freq_rdy_2)  
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 


#1000000
$fclose(write_file1);    
end

输出文本文件为空。我在这段代码中做错了什么？

Answer 1

问题是，当您看到freq_rdy_1或freq_rdy_2的结果时，您只会写入该文件。但是，你永远不会对这些信号产生假设，因为你只设置了一次（在@posedge语句之前）。因此，您永远不会在文件中写任何内容。

也许这就是你要找的东西：

integer write_file1;
initial begin
    write_file1 = $fopen("frequencies.txt","w");
    forever begin
        fork
            begin
                @(posedge testbench.UUT.read_controller.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
            end
            begin
                @(posedge testbench.UUT.read_controller_2.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i);
            end
            begin
                #1_000_000;
                $fclose(write_file1);
            end
        join
    end
end

Answer 2

@toolic：我可以在波形中看到边缘。

通过用一个替换w来解决这个问题而不是

$的fopen（＆＃34; frequencies.txt＆＃34;＆＃34; W＆＃34）;

我写道 $的fopen（＆＃34; frequencies.txt＆＃34;＆＃34;＆＃34）;

虽然我每次运行模拟时都必须删除文件。

其余逻辑使用always块实现。

initial begin 
write_file1 = $fopen("frequencies.txt","a");
end 
always @(posedge. testbench.UUT.read_controller.freq_rdy)         begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
end 
always @(posedge testbench.UUT.read_controller_2.freq_rdy)       begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 
end

这个verilog文件写操作有什么问题

2 个答案: