Question

  module threshold(input[7:0] oLCD_R1,
                  input[7:0] oLCD_G1,
                  input[7:0] oLCD_B1,
                  input[7:0] Rcapture1,
                  input[7:0] Gcapture1,
                  input[7:0] Bcapture1,
                  input oDEN1,
                  output reg[7:0] oLCD_R2,
                  output reg[7:0] oLCD_G2,
                  output reg[7:0] oLCD_B2,
                  output oDEN2,
                  output  [7:0] Rlower,
                  output  [7:0] Rupper,
                  output  [7:0] Glower,
                  output  [7:0] Gupper,
                  output  [7:0] Blower,
                  output  [7:0] Bupper
                );
assign Rlower = Rcapture1;
assign Rupper = Rcapture;
assign oDEN2 = oDEN1;

always @(*)
begin
     if (Rcaputre1 < 30)
     begin
     Rlower = 30;
     end
     if (Rcaputre1 > 225)
       begin
       Rupper = 225;
      end
end 
  begin
  if (
      ( ( Rcapture1 - 30  < oLCD_R1)  &&  (oLCD_R1 < Rcapture1 + 30 ) ) && 
      ( ( Gcapture1 - 30  < oLCD_G1)  &&  (oLCD_G1 < Gcapture1 + 30 ) ) &&
      ( ( Bcapture1 - 30  < oLCD_B1)  &&  (oLCD_B1 < Bcapture1 + 30 ) )
    )   

  begin
 oLCD_R2 = 255;
 oLCD_G2 = 192;
 oLCD_B2 = 0;
 end 
    else 
    begin   
     oLCD_R2 = oLCD_R1;
     oLCD_G2 = oLCD_G1;
     oLCD_B2 = oLCD_B1;
     end 
  end
 endmodule

我正在尝试防止在减法和添加我的Rcapture期间下溢和溢出但是它似乎因为对象的错误而无法工作＆＃39; Rlower＆＃39;在作业的左侧必须有网络类型？我将其声明为output reg为什么我仍然会为Rlower和Rupper

收到此错误

所以改变声明

assign Rlower = Rcapture1 ? Rcapture1 < 30  : Rlower == 30;
assign Rupper = Rcapture1 ? Rcapture1 < 225 : Rupper == 225;

assign Glower = Gcapture1 ? Gcapture1 < 30  : Glower == 30;
assign Gupper = Gcapture1 ? Gcapture1 < 225 : Gupper == 225;

assign Blower = Bcapture1 ? Bcapture1 < 30  : Blower == 30;
assign Bupper = Bcapture1 ? Bcapture1 < 225 : Bupper == 225;

这会停止下溢和溢出问题吗？

Answer 1

regs（和output regs）在always块中分配了值。声明为wire或output的信号被视为＆＃34; net-type＆＃34;，并使用assign语句为其分配值。

将Rlower移至always块，或从声明中删除reg。同样适用于Rupper。

防止下溢和溢出

1 个答案: