在模块声明中选择接口参数

时间:2015-05-12 23:57:14

标签: syntax system-verilog

假设我有一个参数化界面,例如

interface Foo;
    parameter WIDTH=8;
    logic [WIDTH-1:0]data;
endinterface

现在我想在模块中使用宽度为(例如)16的这些接口之一。我怎样才能做到这一点?我试过了

module foo(Foo #(.WIDTH(16)) in, output logic [15:0]out);
    assign out=in.data;
endmodule

但是收到错误:

Error (10170): Verilog HDL syntax error at test.sv(6) near text "#";  expecting ")"

1 个答案:

答案 0 :(得分:5)

当前的SystemVerilog语法BNF不允许您指定接口端口的参数专门化。它将从连接到端口

的实例获取参数化
<?php
if(isset($_POST['submit'])){

// Fetch the variables from the form
$firstname = $_POST['firstname'];
$initial = $_POST['initial'];
$lastname = $_POST['lastname'];
$firm = $_POST['firm'];
$address = $_POST['address'];
$city = $_POST['city'];
$state = $_POST['state'];
$zip = $_POST['zip'];
$phone = $_POST['phone'];
$fax = $_POST['fax'];
$cell = $_POST['cell'];
$email = $_POST['email'];
$website = $_POST['website'];
$university = $_POST['university'];
$degree = $_POST['degree'];
$degreeyr = $_POST['degreeyr'];
$jurisdiction = $_POST['jurisdiction'];
$jurisdictionyr = $_POST['jurisdictionyr'];

//validate
if($firstname != '' && $lastname != '' && $state != '' && $phone != '' && $email != '')
{

//Comma seperate variables in CSV format
$cvsData = $firstname . "," . $initial . "," . $lastname . "," . $firm . "," . $address . "," . $city . "," . $state . "," . $zip . "," . $phone . "," . $fax . "," . $cell . "," . $email . "," . $website . "," . $university . "," . $degree . "," . $degreeyr . "," . $jurisdiction . "," . $jurisdictionyr ."\n";

// Location and Name of CSV file
$fp = fopen("data.csv","a");

if($fp){

// Write the information to the CSV file
fwrite($fp,$cvsData);

// Close the CSV file
fclose($fp);
}
    header('Location: form.php?status=1');
}
else {
    header('Location: form?status=0');
}
}
?>

您可以对特定参数化进行详细检查,如果检查失败,将产生编译错误

module foo(Foo in, output logic [in.WIDTH-1:0] out);
   assign out = in.data;
endmodule          

interface Foo #(
    parameter WIDTH=8
          );
    logic [WIDTH-1:0]data;
endinterface : Foo

module top;
   Foo#(.WIDTH(16)) f();
   logic [15:0] o;
   foo dut(f,o);
endmodule : top

上面的module foo(Foo in, output logic [in.WIDTH-1:0] out); if (in.WIDTH != 16) $error("Width not 16"); assign out = in.data; endmodule 语句不是程序性陈述,而是if