Question

我写了

module booth(num1,num2,prod); 

input [22:0] num1,num2;
output [45:0] prod;
reg[22:0]num1_bar;
reg[46:0]sub_1;
reg [22:0]temp;
reg [2:0]sel;
reg [22:0]add;
reg [22:0]result;
reg [22:0]temp2;


always @* begin
 temp = ~ num1;
 num1_bar = temp + 'b00000000000000000000001;
 sub_1 = {'b00000000000000000000000, num2, 1'b0};
 end

integer i;
always @* begin
    for( i = 0; i < 22; i = i+1) begin
         sel = sub_1[2:0]; 
        if(sel == 2'b10) begin
             add = sub_1[46:24] + num1_bar;
             sub_1 ={add[22],add,sub_1[23:1]};
        end 
        else if(sel == 2'b01) begin
             add = sub_1[46:24] + num1 ;
             sub_1 ={add[22],add,sub_1[23:1]};
        end
        else begin
             sub_1= {sub_1[46] ,sub_1[46:1]};
        end
    end
     temp2 = ~ sub_1[24:1];
     result = 23'b00000000000000000000001 + temp2;
     prod <= result;
end
endmodule

我已经为23 * 23的展位乘数编写了上述代码，但我的代码中有错误。请有人帮帮我。我已经提到了以下错误：

计划摘要新增 xst错误HDLC编译器：247 - ＆＃34; booth.v＆＃34;第59行参考矢量线＆＃39; prod＆＃39;不是合法的法规或变量左值新的 xst错误HDLC编译器：44 - ＆＃34; booth.v＆＃34;第59行阻止任务的非法左侧新增

verilog中的展位乘数误差

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