模拟错误

Question

当我想模拟我的测试时，我不知道为什么Verilog会跟我说error loading design。这段代码在逻辑上有一些错误（它必须添加两个IEEE双精度数，但它没有）：

module adder(sum,a, b);
   input [63:0] a;
   input [63:0] b;
   output reg [63:0] sum;
   reg overflow,underflow;
   real real_a, real_b,sumreal;
   reg[10:0] expa,expb,expab;
   reg [51:0] fa,fb,numbershift;
   reg [10:0]hezar;
   reg[63:0]bigfa,bigfb,fab;
   reg signa,signb;
   reg [70:0]pointerlocation;
   integer i,j;
   always @(a or b) begin
     pointerlocation=52;
     hezar=1023;
     expa=$bitstoreal(a[62:52])-hezar;
     expb=$bitstoreal(b[62:52])-hezar;
     fa=($bitstoreal(a[51:0])/(2^52))+1;
     fb=($bitstoreal(b[51:0])/(2^52))+1;
     signa=a[63];
     signb=b[63];
     //shifting
      if(expa>expb)
       begin
         numbershift=expa-expb;
         bigfb=fb>>numbershift;
         bigfa=fa;
         pointerlocation=pointerlocation+numbershift;
       end
     else if(expa<expb)
       begin
         numbershift=expb-expa;
         bigfa=fa>>numbershift;
         bigfb=fb;
         pointerlocation=pointerlocation+numbershift;
       end
       //sum
       fab=bigfa+bigfb;
       expab=expa;
       //normalize
      while(fab[pointerlocation]==0)
         begin
         fab=fab>>1;
         expab=expab+1;
     end
     //set overflow and underflow
     if(expab>2048)
       overflow=1;
     else if(expab<-2047)
       underflow=1;
  //round
   if(fab[pointerlocation-53]==1)
     begin
     fab=fab+1*(2^(-53));
   end

   fab=(pointerlocation-53)>>fab;
    //normalize
      while(fab[pointerlocation]==0)
         begin
         fab=fab>>1;
         expab=expab+1;
     end
     //set overflow and underflow
     if(expab>2048)
       overflow=1;
     else if(expab<-2047)
       underflow=1;
  //round
   if(fab[pointerlocation-53]==1)
     begin
     fab=fab+1*(2^(-53));
   end

   fab=(pointerlocation-53)>>fab;
   sum={1'b0,$realtobits(expab),fab};
    end
 endmodule

我的测试平台：

module testadder();
   reg [63:0]           a;
   reg [63:0]           b;
   wire [63:0]          sum;   
adder nameofinstace(sum,a,b);
initial begin
   $monitor ($time,,"a= %f b=%f sum = %f", $bitstoreal(a), $bitstoreal(b), $bitstoreal(sum));
   a = {$random(),$random()};
   b = {$random(),$random()};
   #10;
end
endmodule