Question

HI我正在用VHDL构建一个滤波器，当我在DE2板上编程时，声音通过FPGA的输入端口输出到扬声器没问题但是当我将开关移到高电平时激活滤波器没有声音出来。我不知道问题是什么。我将附上代码，希望你可以帮助我找到错误。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

ENTITY lowpass_iir IS
    PORT (readdata_left,readdata_right  : IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
        outL,outR                       : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
        CLOCK_50                        : IN  STD_LOGIC);
END lowpass_iir;

ARCHITECTURE fpga OF lowpass_iir IS
    SIGNAL xL, yL, xR, yR               : SIGNED(23 downto 0):=others=>'0');

BEGIN
    PROCESS (CLOCK_50)    -- Calculates the first coeffitient
        CONSTANT a1:INTEGER:= (1+1/2-1/4-1/8+1/16+1/32+1/64-1/128+1/256+1/512-1/1024+1/2048);
        CONSTANT a2:INTEGER:= -(1+1/2+1/4-1/8-1/16+1/32-1/64+1/128-1/256-1/512-1/1024-1/2048+1/4096);
        CONSTANT a3:INTEGER:= (1/2+1/4-1/8+1/16+1/32+1/64-1/128-1/256-1/512-1/1024+1/2048-1/4096+1/8192);
        CONSTANT a4:INTEGER:= -(1/2-1/4+1/8-1/16+1/32-1/64+1/128-1/256-1/512-1/1024+1/2048-1/4096-1/8192);
        CONSTANT b0:INTEGER:= (1/2-1/4-1/8+1/16+1/32+1/64-1/128+1/256+1/512-1/1024+1/2048);
        CONSTANT b1:INTEGER:= -(1/2+1/4+1/8+1/16-1/32+1/64+1/128-1/256+1/512+1/1024-1/2048-1/4096);
        CONSTANT b2:INTEGER:= (1+1/2-1/4+1/8+1/16-1/32-1/64+1/128-1/256-1/512-1/1024+1/2048-1/4096);
        CONSTANT b3:INTEGER:= -(1/2+1/4+1/8+1/16-1/32+1/64+1/128-1/256+1/512+1/1024-1/2048-1/4096);
        CONSTANT b4:INTEGER:= (1/2-1/4-1/8+1/16+1/32+1/64-1/128+1/256+1/512-1/1024+1/2048);  

        variable yl0,yl1,yl2,yl3,yl4,ylf    : integer;
        variable xl0,xl1,xl2,xl3,xl4        : integer;
        variable yr0,yr1,yr2,yr3,yr4,yrf,c  : integer:=0;
        variable xr0,xr1,xr2,xr3,xr4        : integer:=0;

    BEGIN
        IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
            xL  <= signed(readdata_left);
            xR  <= signed(readdata_right);
            IF (C <4) THEN c:=c+1; END IF;
            case c is
                when 1 =>--y(0)= b0x(0)
                -- LEFT OUTPUT
                xl0 := to_integer(xL);
                yl0 := b0*xl0;
                -- RIGHT OUTPUT
                xr0 := to_integer(xR);
                yr0 := b0*xr0;
                -- output
                ylf  := yl0; 
                yrf := yr0;  

            when 2 => --y(1)= b0x(1)+b1x(0)+a1y(0) 
                xl1 := to_integer(xL);
                yl1 := b0*xl1
                      +b1*xl0+a1*yl0;

                xr1 := to_integer(xR);
                yr1 := b0*xr1
                      +b1*xr0+a1*yr0;
                -- output 
                ylf := yl1;
                yrf := yr1; 

            when 3 =>--y(2)= b0x(2)+b1x(1)+a1y(1)+b2x(0)-a2y(0)
                xl2 := to_integer(xL);
                yl2 := b0*xl2
                      +b1*xl1+a1*yl1
                      +b2*xl0+a2*yl0;

                xr2 := to_integer(xR);
                yr2 := b0*xr2
                      +b1*xr1+a1*yr1
                      +b2*xr0+a2*yr0;
                -- output
                ylf := yl2;
                yrf := yr2; 

            when 4 =>--y(3)= b0x(3)+b1x(2)+a1y(2)+b2x(1)-a2y(1)+b3x(0)+a3y(0)
                xl3 := to_integer(xL);
                yl3:= b0*xl3
                     +b1*xl2+a1*yl2
                     +b2*xl1+a2*yl1
                     +b3*xl0+a3*yl0;

                xr3 := to_integer(xR);
                yr3 := b0*xr3
                      +b1*xr2+a1*yr2
                      +b2*xr1+a2*yr1
                      +b3*xr0+a3*yr0;
                -- output  
                ylf := yl3;
                yrf := yr3;         

            when others =>--y(n)= b0x(n)+b1x(n-1)+a1y(n-1)+b2x(n-2)-a2y(n-2)+b3x(n-3)+a3y(n-3)  
                xl4 := to_integer(xL);
                yl4:= b0*xl4
                     +b1*xl3+a1*yl3
                     +b2*xl2+a2*yl2
                     +b3*xl1+a3*yl1
                    +b4*xl0+a4*yl0;
                xl0 := xl1;
                xl1 := xl2;
                xl2 := xl3;
                xl3 := xl4;
                yl0 := yl1;
                yl1 := yl2;
                yl2 := yl3;
                yl3 := yl4;

                xr4 := to_integer(xR);
                yr4 := b0*xr4
                      +b1*xr3+a1*yr3
                      +b2*xr2+a2*yr2
                      +b3*xr1+a3*yr1
                      +b4*xr0+a4*yr0;
                xr0 := xr1;
                xr1 := xr2;
                xr2 := xr3;
                xr3 := xr4;
                yr0 := yr1;
                yr1 := yr2;
                yr2 := yr3;
                yr3 := yr4;
                -- output
                ylf := yl4;
                yrf := yr4;         
            end case;
        END IF;
    END PROCESS;

    yL <= TO_SIGNED(ylf,24);
    yR <= TO_SIGNED(yrf,24);
    outL <= STD_LOGIC_VECTOR(yL); -- Left output 
    outR <= STD_LOGIC_VECTOR(yR); -- Right output 

END fpga;

Answer 1

嗨，这些任命不起作用：

yL <= TO_SIGNED(ylf,24);
yR <= TO_SIGNED(yrf,24);

确实，你宣布了ylf＆amp; yrf作为流程中的变量。所以他们不能在这个过程之外使用。

在DE2 FPGA上过滤声音

1 个答案: