Question

如何初始化阵列Save_state？该语句在输出中给出X值：

reg [9:0] count 
 reg [9:0] Save_state [0: 1024]; 

 always @ (posedge Clock )
 Count <=count+1 ;
 Save_state[count] <=count ;

Answer 1

您可以使用重置端口初始化count和save_state，例如以下代码：

integer i;
reg [9:0] count;
reg [9:0] save_state [0:1024];

always @(posedge clock or posedge reset) begin
    if (reset) begin
        count <= 0;
        for (i=0; i<=1024; i=i+1)
            save_state[i] <= 0;
    end
    else begin
        count <= count + 1;
        save_state[count] <= count;
    end
end

else块中的两个语句同时应用于always块的末尾。

Answer 2

您也可以使用初始块。这在模拟中是允许的，并且可以在某些架构上进行综合（Xilinx FPGA和CPLD支持寄存器初始化）

reg [9:0] count 
reg [9:0] Save_state [0: 1024]; 

integer i;
initial begin
  count = 0;
  for (i=0;i<=1024;i=i+1)
    Save_state[i] = 0;
end

always @ (posedge Clock ) begin
   count <= count + 1;
   Save_state[count] <= count;
end

虽然对于这个特殊的例子，Save_state数组的元素总是具有相同的值，你可以这样做（可在Xilinx和Altera，AFAIK上合成）：

reg [9:0] Save_state [0: 1024]; 

integer i;
initial begin
  for (i=0;i<=1024;i=i+1)
    Save_state[i] = i[9:0];
end

在模拟开始时，Save_state已经存储了值0,1,2，...，1023。

在Verilog中初始化数组

2 个答案: