用VHDL签署MOD

Question

我正在尝试编写一个VHDL代码来进行32位除法和模块（MOD）...... 无符号部分有效，但是当我选择有符号数时，除法结果是正确的，而剩余部分不正确！ 为了前-10 mod 3＆gt;＆gt;＆gt;＆gt;结果= -3＆amp;剩余= 2！ 那有什么不对？

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity DivEx is
port(
    X   : in STD_LOGIC_VECTOR(31 downto 0);
    DIV_SU : IN std_logic ;
    Y   : in STD_LOGIC_VECTOR(31 downto 0);
    R   : out STD_LOGIC_VECTOR(31 downto 0);
    q   : out STD_LOGIC_VECTOR(31 downto 0)
);
end DivEx;

architecture Behavioral of DivEx is
begin

R <= (std_logic_vector(to_signed(to_integer(signed(X) / signed(Y)),32))) WHEN  (DIV_SU = '1') else (std_logic_vector(to_unsigned(to_integer(unsigned(X) / unsigned(Y)),32)));
q <= std_logic_vector(to_signed(to_integer(signed(X) mod signed(Y)),32)) WHEN  (DIV_SU = '1') else std_logic_vector(to_unsigned(to_integer(unsigned(X) / unsigned(Y)),32));

end Behavioral;